Patents by Inventor Vincent Tso
Vincent Tso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7834672Abstract: A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.Type: GrantFiled: February 10, 2007Date of Patent: November 16, 2010Assignee: Exar CorporationInventors: Christopher G. Arcus, Vincent Tso, James Ho
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Publication number: 20070189429Abstract: A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.Type: ApplicationFiled: February 10, 2007Publication date: August 16, 2007Applicant: Exar CorporationInventors: Christopher Arcus, Vincent Tso, James Ho
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Publication number: 20060238263Abstract: To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.Type: ApplicationFiled: June 30, 2006Publication date: October 26, 2006Applicant: Exar CorporationInventors: Vincent Tso, James Ho
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Publication number: 20060066359Abstract: To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Applicant: Exar CorporationInventors: Vincent Tso, James Ho
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Publication number: 20050285637Abstract: A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.Type: ApplicationFiled: June 28, 2004Publication date: December 29, 2005Applicant: Exar CorporationInventors: Timothy Lu, Vincent Tso
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Patent number: 6960942Abstract: Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control terminals coupled to receive a respective plurality of phase selection signals. The circuit is configured to output a first selected clock signal from the plurality of clock signals in response to a first combination of the phase selection signals, and further configured to switch from the first selected clock signal to a second selected clock signal in response to a second combination of the phase selection signal. The circuit disengages the first clock signal after the second phases selection signal is engaged.Type: GrantFiled: May 18, 2001Date of Patent: November 1, 2005Assignee: Exar CorporationInventors: Bahram Ghaderi, Vincent Tso, Sunil Jaggia, Johnny Lee
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Publication number: 20020174374Abstract: Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control terminals coupled to receive a respective plurality of phase selection signals. The circuit is configured to output a first selected clock signal from the plurality of clock signals in response to a first combination of the phase selection signals, and further configured to switch from the first selected clock signal to a second selected clock signal in response to a second combination of the phase selection signal. The circuit disengages the first clock signal after the second phases selection signal is engaged.Type: ApplicationFiled: May 18, 2001Publication date: November 21, 2002Inventors: Bahram Ghaderi, Vincent Tso, Sunil Jaggia, Johnny Lee