Patents by Inventor Vincent Von Kaenel

Vincent Von Kaenel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070229054
    Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.
    Type: Application
    Filed: May 25, 2007
    Publication date: October 4, 2007
    Inventors: Daniel Dobberpuhl, Vincent von Kaenel
  • Publication number: 20070057735
    Abstract: In one embodiment, an apparatus comprises a voltage-controlled oscillator (VCO) that comprises a circuit coupled to receive an input control voltage to the VCO and configured to generate a second voltage responsive to the input control voltage, a summator coupled to receive the input control voltage and the second voltage, and an oscillator coupled to receive the output voltage of the summator. The summator is configured to combine the input control voltage and the second voltage to generate the output voltage. The oscillator is configured to oscillate an output signal, wherein a frequency of oscillation of the output signal is controlled by the output voltage of the summator.
    Type: Application
    Filed: September 12, 2005
    Publication date: March 15, 2007
    Applicant: P.A. Semi, Inc.
    Inventor: Vincent von Kaenel
  • Publication number: 20070001697
    Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 4, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Daniel Dobberpuhl, Vincent von Kaenel
  • Publication number: 20070001747
    Abstract: In one embodiment, an apparatus is provided for a system including an integrated circuit coupled to a node to receive a supply voltage and having bypass capacitors coupled in parallel with the integrated circuit to the node. The apparatus comprises a first capacitor, a switch coupled to the first capacitor, and a voltage source configured to charge the first capacitor. The switch is coupled to receive a control signal that is asserted, during use, if the supply voltage to an integrated circuit is to be increased. The switch is configured to electrically couple the first capacitor to the node in response to an assertion of the control signal. When electrically coupled to the node, the first capacitor supplies charge to the bypass capacitors. A system comprising the apparatus, the node, the integrated circuit, and the bypass capacitors is also contemplated in some embodiments.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 4, 2007
    Applicant: P.A. Semi, Inc.
    Inventor: Vincent von Kaenel
  • Publication number: 20070002636
    Abstract: In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 4, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Brian Campbell, Vincent von Kaenel, Daniel Murray, Gregory Scott, Sribalan Santhanam
  • Patent number: 7038487
    Abstract: A multi-function interface includes a digital interface module and a configurable output impedance module. The digital interface module is operably coupled to pass a first type of input signal when the multi-function interface is in a first mode and operably coupled to pass a second type of input signal when the multi-function interface is in a second mode. The configurable output impedance module is operably coupled to the digital interface to provide a first output impedance when the multi-function interface is in the first mode and to provide a second output impedance when the multi-function interface is in the second mode.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: May 2, 2006
    Assignee: Broadcom Corporation
    Inventors: Joseph Ingino, Vincent Von Kaenel
  • Publication number: 20050218957
    Abstract: In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 6, 2005
    Inventors: Haluk Konuk, Vincent von Kaenel, Dai Le
  • Publication number: 20050030061
    Abstract: A multi-function interface includes a digital interface module and a configurable output impedance module. The digital interface module is operably coupled to pass a first type of input signal when the multi-function interface is in a first mode and operably coupled to pass a second type of input signal when the multi-function interface is in a second mode. The configurable output impedance module is operably coupled to the digital interface to provide a first output impedance when the multi-function interface is in the first mode and to provide a second output impedance when the multi-function interface is in the second mode.
    Type: Application
    Filed: September 17, 2004
    Publication date: February 10, 2005
    Inventors: Joseph Ingino, Vincent Von Kaenel
  • Patent number: 6809547
    Abstract: A multi-function interface includes a digital interface module, a configurable driver module, and a configurable output impedance module. The digital interface module is operably coupled to pass a 1st type of input signal when the interface is in a 1st mode and operably coupled to pass a 2nd type of input signal when the interface is in a 2nd mode. The configurable driver module is operably coupled to amplify the 1st type of input signal when the interface is in the 1st mode and to amplify the 2nd type of input signal when the interface is in the 2nd mode. The configurable output impedance module is coupled to the configurable driver module to provide a 1st output impedance of the interface when the interface is in the 1st mode and to provide a 2nd output impedance when the interface is in the 2nd mode.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: October 26, 2004
    Assignee: Broadcom, Corp.
    Inventors: Joseph Ingino, Vincent Von Kaenel
  • Publication number: 20030117166
    Abstract: A multi-function interface includes a digital interface module, a configurable driver module, and a configurable output impedance module. The digital interface module is operably coupled to pass a 1st type of input signal when the interface is in a 1st mode and operably coupled to pass a 2nd type of input signal when the interface is in a 2nd mode. The configurable driver module is operably coupled to amplify the 1st type of input signal when the interface is in the 1st mode and to amplify the 2nd type of input signal when the interface is in the 2nd mode. The configurable output impedance module is coupled to the configurable driver module to provide a 1st output impedance of the interface when the interface is in the 1st mode and to provide a 2nd output impedance when the interface is in the 2nd mode.
    Type: Application
    Filed: November 27, 2002
    Publication date: June 26, 2003
    Inventors: Joseph Ingino, Vincent Von Kaenel
  • Patent number: 6104251
    Abstract: The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: August 15, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Delvan A. Ramey, Vincent von Kaenel
  • Patent number: 5682118
    Abstract: The control circuit includes a reference MOS transistor (24) on which preermined operating characteristics are imposed. Circuitry (21, 22, 23) is provided for comparing an operating characteristic of the transistor (24) with a reference value (V.sub.tnref) so as to produce a control voltage. This voltage, after adaptation, is applied to the transistor (24) so as to fix the threshold voltage (V.sub.th) thereof, in such a way as to maintain the operating characteristics of the transistor (24). This same threshold voltage is then imposed on all the transistors of the logic circuit with which the control circuit is associated. This control circuit makes it possible particularly to reduce the consumption of said logic circuit.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: October 28, 1997
    Assignee: C.S.E.M. Centre Suisse d'Electronique et de Microtechnique S.A.
    Inventors: Vincent Von Kaenel, Matthijs Daniel Pardoen
  • Patent number: 5485116
    Abstract: The invention concerns a power diverting circuit for creating a supply voltage for a signal processing circuit from a source of data signals each having a high or a low potential respectively corresponding to a first or a second logic state. The circuit comprises a first terminal for receiving the data signals, a second terminal for providing the supply voltage, a switch coupled between the first terminal and the second terminal for selectively connecting and disconnecting the first terminal and the second terminal, and an inverter for inverting the state of the data signals. The inverter, which has an input terminal connected to the first terminal and an output terminal for providing the inverted data signals to the signal processing circuit, is responsive to the state of the data signals received at the first terminal to control the operation of said switch means.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: January 16, 1996
    Assignee: CSEM Centre Suisse d'Electronique et de Microtechnique SA - Recherche et Developpement
    Inventors: Stefan Cserveny, Evert Dijkstra, Vincent von Kaenel