Patents by Inventor Vincent Weihao HSIAO

Vincent Weihao HSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for parasitic-aware capacitor sizing and layout generation
    Patent number: 10635771
    Abstract: A method for parasitic-aware capacitor sizing and layout generation is proposed, which is executed by a computer, the method comprising using the computer to perform the following: creating a capacitor sizing and parasitic matching sequence to represent a unit capacitor size, routing topology and routing patterns of a plural of nets in a capacitor network. Next, a shielding assignment is performed to create a number of shielding portions of each net in the plural of nets. Then, a fitness evaluation of configurations of the capacitor sizing and parasitic matching sequence is performed. A shielding net routing is performed to compensate unmatched parasitic capacitance of the configurations of the capacitor sizing and parasitic matching sequence.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: April 28, 2020
    Assignee: AnaGlobe Technology, Inc.
    Inventors: Po-Hung Lin, Vincent Weihao Hsiao, Chun-Yu Lin, Nai-Chen Chen, Yu-Tsang Hsieh
  • Method for Parasitic-Aware Capacitor Sizing and Layout Generation
    Publication number: 20190114381
    Abstract: A method for parasitic-aware capacitor sizing and layout generation is proposed, which is executed by a computer, the method comprising using the computer to perform the following: creating a capacitor sizing and parasitic matching sequence to represent a unit capacitor size, routing topology and routing patterns of a plural of nets in a capacitor network. Next, a shielding assignment is performed to create a number of shielding portions of each net in the plural of nets. Then, a fitness evaluation of configurations of the capacitor sizing and parasitic matching sequence is performed. A shielding net routing is performed to compensate unmatched parasitic capacitance of the configurations of the capacitor sizing and parasitic matching sequence.
    Type: Application
    Filed: October 18, 2017
    Publication date: April 18, 2019
    Inventors: Po-Hung LIN, Vincent Weihao HSIAO, Chun-Yu LIN, Nai-Chen CHEN, Yu-Tsang HSIEH