Abstract: An integrated circuit (IC) including an IC cell arranged in a row of IC cells, wherein the IC cells in the row have substantially the same height, wherein the IC cell includes a portion of an intercell metal interconnect terminating at the IC cell at a metal layer or extending entirely through the IC cell on the metal layer and electrically connecting together a pair of nodes of a pair of IC cells, respectively.

Abstract: An integrated circuit (IC), including a first integrated circuit (IC) cell configured to perform a defined operation on a first input signal to generate a first output signal, wherein the first IC cell includes a first metal configured to receive the first input signal or output the first output signal; and a second IC cell configured to perform the defined operation on a second input signal to generate a second output signal, wherein the second IC cell includes a second metal configured to receive the second input signal or the second output signal, wherein the second metal is located substantially in the same location within the second IC cell as the first metal is located within the first IC cell, and wherein the first and second metals are configured differently based on differences in first and second intercell metal interconnects to which the first and second metals electrically connect, respectively.

Abstract: An integrated circuit (IC) including an IC cell arranged in a row of IC cells, wherein the IC cells in the row have substantially the same height, wherein the IC cell includes a portion of an intercell metal interconnect terminating at the IC cell at a metal layer or extending entirely through the IC cell on the metal layer and electrically connecting together a pair of nodes of a pair of IC cells, respectively.

Abstract: An integrated circuit (IC), including a first integrated circuit (IC) cell configured to perform a defined operation on a first input signal to generate a first output signal, wherein the first IC cell includes a first metal configured to receive the first input signal or output the first output signal; and a second IC cell configured to perform the defined operation on a second input signal to generate a second output signal, wherein the second IC cell includes a second metal configured to receive the second input signal or the second output signal, wherein the second metal is located substantially in the same location within the second IC cell as the first metal is located within the first IC cell, and wherein the first and second metals are configured differently based on differences in first and second intercell metal interconnects to which the first and second metals electrically connect, respectively.