Patents by Inventor Vincenzo Condorelli
Vincenzo Condorelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10680023Abstract: Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described.Type: GrantFiled: March 19, 2019Date of Patent: June 9, 2020Assignee: ams Sensors Singapore Pte. Ltd.Inventors: Hartmut Rudmann, Mario Cesana, Jens Geiger, Peter Roentgen, Vincenzo Condorelli
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Patent number: 10605920Abstract: The present disclosure describes refresh control methods for generating distance data and optoelectronic modules that are operable to provide distance information at a predetermined refresh rate, but with a reduction in overall power consumption attributable to the distance determinations.Type: GrantFiled: January 13, 2017Date of Patent: March 31, 2020Assignee: ams Sensors Singapore Pte. Ltd.Inventors: Yang Liu, Vincenzo Condorelli
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Publication number: 20190326340Abstract: Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described.Type: ApplicationFiled: March 19, 2019Publication date: October 24, 2019Applicant: ams Sensors Singapore Pte. Ltd.Inventors: Hartmut Rudmann, Mario Cesana, Jens Geiger, Peter Roentgen, Vincenzo Condorelli
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Patent number: 10283542Abstract: Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described.Type: GrantFiled: June 14, 2017Date of Patent: May 7, 2019Assignee: ams Sensors Singapore Pte. Ltd.Inventors: Hartmut Rudmann, Mario Cesana, Jens Geiger, Peter Roentgen, Vincenzo Condorelli
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Patent number: 10255450Abstract: Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.Type: GrantFiled: December 4, 2017Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd W. Arnold, Mark A. Check, Vincenzo Condorelli
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Patent number: 10108569Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.Type: GrantFiled: September 3, 2015Date of Patent: October 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark A. Check, Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez
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Patent number: 10102165Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.Type: GrantFiled: November 25, 2014Date of Patent: October 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark A. Check, Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez
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Publication number: 20180101689Abstract: Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.Type: ApplicationFiled: December 4, 2017Publication date: April 12, 2018Inventors: Todd W. ARNOLD, Mark A. CHECK, Vincenzo CONDORELLI
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Patent number: 9875367Abstract: Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.Type: GrantFiled: February 23, 2017Date of Patent: January 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd W. Arnold, Mark A. Check, Vincenzo Condorelli
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Publication number: 20170287963Abstract: Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described.Type: ApplicationFiled: June 14, 2017Publication date: October 5, 2017Applicant: Heptagon Micro Optics Pte. Ltd.Inventors: Hartmut Rudmann, Mario Cesana, Jens Geiger, Peter Roentgen, Vincenzo Condorelli
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Patent number: 9711552Abstract: Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described.Type: GrantFiled: August 11, 2015Date of Patent: July 18, 2017Assignee: Heptagon Micro Optics Pte. Ltd.Inventors: Hartmut Rudmann, Mario Cesana, Jens Geiger, Peter Roentgen, Vincenzo Condorelli
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Publication number: 20170199276Abstract: The present disclosure describes refresh control methods for generating distance data and optoelectronic modules that are operable to provide distance information at a predetermined refresh rate, but with a reduction in overall power consumption attributable to the distance determinations.Type: ApplicationFiled: January 13, 2017Publication date: July 13, 2017Applicant: Heptagon Micro Optics Pte. Ltd.Inventors: Yang Liu, Vincenzo Condorelli
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Patent number: 9703973Abstract: Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.Type: GrantFiled: April 28, 2015Date of Patent: July 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd W. Arnold, Mark A. Check, Vincenzo Condorelli
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Publication number: 20170161510Abstract: Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.Type: ApplicationFiled: February 23, 2017Publication date: June 8, 2017Inventors: Todd W. Arnold, Mark A. Check, Vincenzo Condorelli
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Patent number: 9575769Abstract: A method for updating code images in a system includes booting a first image of a code with a sub-system processor, receiving a second image of the code, performing a security and reliability check of the second image of the code with the sub-system processor, determining whether the security and reliability check of the second image of the code is successful, storing the second image of the code in a first memory device responsive to determining that the security and reliability check of the second image of the code is successful, designating the second image of the code as an active image, and sending the second image of the code to a second memory device, the second memory device communicatively connected with the first memory device and a main processor.Type: GrantFiled: April 6, 2015Date of Patent: February 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vincenzo Condorelli, Silvio Dragone, William Santiago-Fernandez, Tamas Visegrady
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Patent number: 9535656Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.Type: GrantFiled: March 14, 2014Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vincenzo Condorelli, Silvio Dragone, William Santiago Fernandez, Nihad Hadzic, Andrew R. Ranck
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Publication number: 20160321662Abstract: Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.Type: ApplicationFiled: April 28, 2015Publication date: November 3, 2016Inventors: Todd W. Arnold, Mark A. Check, Vincenzo Condorelli
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Patent number: 9471276Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.Type: GrantFiled: April 5, 2016Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vincenzo Condorelli, Silvio Dragone, William Santiago Fernandez, Nihad Hadzic, Andrew R. Ranck
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Publication number: 20160210119Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.Type: ApplicationFiled: April 5, 2016Publication date: July 21, 2016Inventors: Vincenzo Condorelli, Silvio Dragone, William Santiago Fernandez, Nihad Hadzic, Andrew R. Ranck
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Publication number: 20160147685Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.Type: ApplicationFiled: September 3, 2015Publication date: May 26, 2016Inventors: Mark A. Check, Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez