Abstract: The present invention is a monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type, which cells allow the signal paths between signal lines of the elementary modules to be programmed and re-programmed. Preferably, the flash memory cells are Fowler-Nordheim Effect cells.

Abstract: A staircase adaptive voltage generator circuit comprising a first capacitor connected between a first voltage reference and an output operational amplifier, through first and second switches, respectively. The terminals of the capacitor are also connected to a second voltage reference through third and fourth switches, respectively. A second capacitor, in series with a fifth switch, is connected in parallel to the first capacitor.

Abstract: Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels.

Abstract: A serial dichotomic method for sensing multiple-level non-volatile memory cells which can take one of m=2.sup.n (n>=2) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, and for: a) comparing the cell current with a reference current which has a value comprised between a minimum value and a maximum value of said plurality of m cell current values, thus dividing said plurality of cell current values into two sub-pluralities of cell current values, and determining the sub-plurality of cell current values to which the cell current belongs; b) repeating the step a) until the sub-plurality of cell current values to which the cell current belongs comprises only one cell current value, which is the value for the current of the memory cell to be sensed.

Abstract: A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator.

Abstract: A null consumption CMOS switch which may be set by nonvolatile programming is formed by a pair of complementary transistors preferably having a common drain and a common gate. The common gate is coupled to the floating gate a programmable and erasable, nonvolatile memory cell. The common gate/floating gate coupling can be a unitary floating gate structure. The floating gate directly drives the ON or OFF states of the two complementary transistors. On an output node of the switch, represented by the common drain of the pair of transistors, a signal present on a source node of one or the other of the two complementary transistors is replicated. The state of charge of the floating gate, imposed by programming or erasing, may be such as to reach advantageously a potential higher than the supply voltage or lower than the ground potential of the circuit. Different embodiments, such as a polarity selection, a path selector, a TRISTATE selector, and a logic gate selector are described.

Abstract: A programmable logic device has an architecture which permits to implement logic functions through loopable multi-levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks.

Abstract: An integrated analog circuit having a circuit topology and intrinsic characteristics which may be selected by digital control means is formed by batteries of similar circuit components arranged substantially in parallel or in a matrix array, anyone of which may be isolated or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative integrated switch. A dedicated nonvolatile memory, integrated on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selected a particlar component or more components of each of said batteries of functionally similar components, and/or selecting a certain interconnection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics.

Abstract: CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters connected in cascade, the input of the first inverter being connected to the input of the circuit. Using two signal inverting stages or inverters for mirroring the input signal on the gate of the load P-channel transistor of the circuit pair permits the defining of the triggering threshold of the circuit with great freedom, the obtaining of a greater switching speed and the reduction of power dissipation under stand-by conditions. The invention is particularly suited for HCT circuits.

Abstract: The influence of the resistance of the connection between a terminal of voltage limiting diodes against discharges of electrostatic nature which may hit a pad of an integrated circuit and a respective common potential node of the integrated circuit (supply or ground node) is unsuspectably critical. A resistance of just few ohms may depress the maximum tolerable discharge voltage by several thousands volts and the relationship between such two parameters is hyperbolic. Such a critical resistance may advantageously be reduced by utilizing more levels of metallization purposely connected in parallel and/or by "shifting" the protection diodes near the real (and not virtual) common potential node of the circuit or by utilizing "ring" metallizations over different levels for both the common potential nodes of the circuit.

Abstract: Two circuits carry out the beating of a modulated signal, with first and second signals, respectively, each having substantially the same frequency as the carrier of the modulated signal but phased-shifted relative to one another by 90.degree.. A commutator controlled by a control circuit alternately selects the signals resulting from the beating. The selection is responsive to the amplitudes of the signals in order to avoid losses of information due to amplitude peaks under a prefixed threshold which may be caused by frequency differences between the signals which are beat.

Abstract: A nonvolatile memory of the electrically alterable kind comprises an orthogonal array of cells each including a floating-gate IGFET and an enhancement IGFET in series. For the programming or the reading of a selected cell, lying at the intersection of a row and a column of the array, a common gate lead for all the enhancement IGFETs of the row and a common drain lead for all the enhancement IGFETs of the column are energized with voltage dependent on the desired kind of operation. To write a bit in a cell, its floating gate is progressively charged in a succession of steps separated by reading operations to check on the conduction threshold of the cell; the charging ends when that threshold reaches a predetermined storage level. To cancel a written bit, the floating gate is progressively discharged in a succession of steps again separated by reading operations; the discharging is terminated when the conduction threshold reaches a predetermined cancellation level.

Abstract: Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal.

Abstract: Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal.

Abstract: A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator.