Abstract: Compensation for an RF detector includes components having different order temperature functions. The components are combined and may be adjusted by various numbers of user-accessible terminals to provide individual adjustment for factors such as operating frequency. In some embodiments, first and second-order temperature functions are generated independently and combined to provide a polynomial function of temperature with coefficients that may be adjusted. In other embodiments, the outputs of the function generators may be more complex functions of temperature with various adjustable parameters.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: An interpolated variable gain amplifier (VGA) utilizes multiple active feedback cells. The active feedback cells may be implemented as transconductance (gm) cells that replicate gm cells in the interpolated input stages.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A logarithmic amplifier is compensated by a feedback loop. The feedback loop may control a series of detector cells in response to an output from one or more of the detector cells. The feedback loop may be used to provide frequency compensation to the log amp by adjusting the bias currents to the detector cells. One detector cell may be arranged to generate a limiting signal while another detector cell is arranged to generate a zero signal. By arranging the feedback loop to adjust the bias cell so as to maintain the difference between the limit signal and the zero signal at a constant value, the output swing of the detector cells is held constant, thereby stabilizing the slope of the log amp.

Abstract: Methods and apparatus for correcting for circuit self-heating replicate a thermal characteristic of a component that may be coupled to a bias circuit. A bias circuit may include replication component coupled to a reference cell. The replication component may be included in a feedback loop with the reference cell to improve accuracy.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: Methods and apparatus for correcting for circuit self-heating replicate a thermal characteristic of a component that may be coupled to a bias circuit. A bias circuit may include replication component coupled to a reference cell. The replication component may be included in a feedback loop with the reference cell to improve accuracy.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A buffer circuit includes a delay circuit which is interposed between a signal source and a following circuit. The delay circuit propagates a signal from an input to an output; the signal has associated desired timing relationships between its rising and falling edges. The delay circuit controls the propagation delays of the signal's rising and falling edges such that when the signal arrives at a selected downstream node, it has the desired timing relationships. The delay circuit adjusts the propagation delays in accordance with two correction signals: one which reduces errors induced by imperfections in the signal path through which the test signal propagates, and one to reduce errors due to thermal effects that arise when propagating a periodic test signal having a duty cycle other than 50% through the signal path.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: Differential-signal gate structures are provided in which first and second current-switching modules are coupled to first and second electrical loads with the differential input ports of the modules cross coupled. Although each of the modules separately exhibits an increased propagation-delay response to one input signal sequence, they are never simultaneously exposed to this sequence because of the cross coupling of the input ports. Accordingly, these gate structures have significantly reduced propagation-delay variations.

Abstract: D flip-flop structures are provided which respond to a DATA signal and a clock (CLK) signal by generating an output signal whose state during each clock pulse is that of the DATA signal at that pulse's leading edge and whose state between clock pulses is reset to a selected logic value. Accordingly, these flip-flops can function (e.g., monitor events in the DATA signal or generate sequences of trigger pulses) at the clock rate.

Abstract: A high speed, multiple input restrictive OR circuit with fully differential inputs and output is used in applications in which only one input can be active at a time. N differential voltage inputs are converted into N corresponding differential current signals of unit current values. The current signals corresponding to active complement input signals are summed together, with a compensation current equal to (N−1) current units subtracted from the total. The resulting compensated complement currents together with any active input current form a single differential current that indicates the logic state at the input. This differential current is preferably converted to a buffered output differential voltage in an output stage. For high accuracy applications, a common unit reference current is used to generate both a scaled compensation current and unit input stage source currents.