Abstract: Methods, systems, and devices for techniques for memory cell refresh are described. A memory system may support a low power mode in which the memory system may periodically perform a refresh operation. In some cases, the memory system and a host system coupled with the memory system may support a command to enter the low power mode. As part of the low power mode, the memory system may receive at least one power supply of one or more supported power supplies, such that the memory system may remain active and thus periodically perform the refresh operation. In some cases, the memory system may adjust the periodicity of the refresh operation in response to detecting a triggering event, such as a high temperature, a large system age, or a combination thereof.

Abstract: Methods, systems, and devices for metadata allocation in memory systems are described. Different blocks of a memory device of the memory system may be utilized for storing different types of data. For example, a first block may be utilized to store journaling data and a second block to store data (e.g., user data) received from a host system. The first block may include memory cells operable as high endurance single-level cells, and may be configured to support a high frequency of write operations of data with low retention rates. Additionally, the second set of block may include memory cells (e.g., a high density of memory cells) operable as multiple-level cells, and may be configured to retain large quantities of data.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: Methods, systems, and devices for managing information protection schemes in memory systems are described. A memory device may dynamically select an information protection scheme from a set of information protection schemes. In some examples, the memory device may identify a quantity of defective blocks in each plane associated with a control. The memory device may then identify a quantity of planes that satisfy a block threshold. In some cases, the memory device may select an information protection scheme using the quantity of planes. The information protection scheme may be an example of a redundant array of independent nodes scheme, and may indicate a quantity of planes used in performing a protected write operation.

Abstract: Methods, systems, and devices for techniques for memory cell refresh are described. A memory system may support a low power mode in which the memory system may periodically perform a refresh operation. In some cases, the memory system and a host system coupled with the memory system may support a command to enter the low power mode. As part of the low power mode, the memory system may receive at least one power supply of one or more supported power supplies, such that the memory system may remain active and thus periodically perform the refresh operation. In some cases, the memory system may adjust the periodicity of the refresh operation in response to detecting a triggering event, such as a high temperature, a large system age, or a combination thereof.

Abstract: Methods, systems, and devices for techniques to refresh memory systems operating in low power states are described. The memory system may operate in a first power mode that includes deactivation of a voltage rail that supplies power to the memory system. The memory system may receive the power over the voltage rail during a time period that the memory system is operating in the first power mode. In some cases, the memory system may determine that the power may be received for a duration and a command is not received during that duration. The memory system may perform a self-refresh operation based on determining that the duration indicated by the timer expires without receiving a command.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: Methods, systems, and devices for managing information protection schemes in memory systems are described. A memory device may dynamically select an information protection scheme from a set of information protection schemes. In some examples, the memory device may identify a quantity of defective blocks in each plane associated with a control. The memory device may then identify a quantity of planes that satisfy a block threshold. In some cases, the memory device may select an information protection scheme using the quantity of planes. The information protection scheme may be an example of a redundant array of independent nodes scheme, and may indicate a quantity of planes used in performing a protected write operation.

Abstract: An example method for managing a memory device includes a non-volatile memory. The example method further includes providing a first time-stamp to the memory device, wherein the first time-stamp is a power-down time-stamp of the memory device, storing the first time-stamp, associating the first time-stamp with at least one region of the non-volatile memory, providing a second time-stamp to the memory device, wherein the second time-stamp is a subsequent power-up time-stamp of the memory device, associating the second time-stamp with the at least one region of the non-volatile memory, determining a difference time between the first time-stamp and the second time-stamp, and, based on the difference time, performing a refresh operation of the at least one region of the non-volatile memory. Further, a related memory device is disclosed, as well as a method for measuring the off-time of a memory device.

Abstract: A method includes determining respective health characteristic values of blocks of non-volatile memory cells, determining, based on the respective health characteristic values and at least one effective health factor of the blocks of the non-volatile memory cells, effective respective health characteristic values of the blocks of non-volatile memory cells, and based on the effective respective health characteristic values, performing a media management operation involving a block of non-volatile memory cells of the blocks of non-volatile memory cells having an effective respective health characteristic value that is greater than a health criterion.

Abstract: Systems, apparatuses, and methods to secure remote collection of memory diagnostics data generated during operations of memory cells configured in a memory device connected to a host system. The diagnostics data is stored in a secure memory region within the memory device, which controls access to the secure memory region based on cryptography. After a communication connection is established, via the host system and between the memory device and a security server having a privilege to access the secure memory region, the diagnostics data can be transmitted from the memory device to the security server in an encrypted form over the communication connection.

Abstract: A memory device can dynamically select a voltage step size for programming (i.e., charging) memory cells. The memory device can increase the voltage step size to reduce programming time or decrease the voltage step size to reduce errors. The memory device can identify device conditions, such as temperature or amount of use (e.g., a count of program/erase cycles). The memory device can increase the voltage step size when the device conditions are less likely to cause errors (e.g., in a middle temperature range or below a threshold number of program/erase cycles) or can decrease the voltage step size when the device conditions are more likely to cause errors (e.g., in a high or low temperature range or above a threshold number of program/erase cycles).

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: The present disclosure relates to a method for managing a memory device including a non-volatile memory, the method comprising providing a first time-stamp to the memory device, wherein the first time-stamp is a power-down time-stamp of the memory device, storing the first time-stamp, associating the first time-stamp with at least one region of the non-volatile memory, providing a second time-stamp to the memory device, wherein the second time-stamp is a subsequent power-up time-stamp of the memory device, associating the second time-stamp with said at least one region of the non-volatile memory, determining a difference time between the first time-stamp and the second time-stamp, and, based on said difference time, performing a refresh operation of said at least one region of the non-volatile memory. A related memory device is also disclosed, as well as a specific method for measuring the off-time of a memory device.

Abstract: A memory device can dynamically select a voltage step size for programming (i.e., charging) memory cells. The memory device can increase the voltage step size to reduce programming time or decrease the voltage step size to reduce errors. The memory device can identify device conditions, such as temperature or amount of use (e.g., a count of program/erase cycles). The memory device can increase the voltage step size when the device conditions are less likely to cause errors (e.g., in a middle temperature range or below a threshold number of program/erase cycles) or can decrease the voltage step size when the device conditions are more likely to cause errors (e.g., in a high or low temperature range or above a threshold number of program/erase cycles).