Abstract: The present invention relates to a method for bug localisation in an RTL description, the RTL description corresponding to a design. The method comprises the steps of identifying a failing property; obtaining a counterexample corresponding to the failing property; obtaining a plurality of supportive counterexamples, by iteratively modifying the failing property with signal-value combinations selected from the counterexample; mining assertions based on the plurality of supportive counterexamples; filtering and ranking the mined assertions for removing redundant assertions, and obtaining a filtered set of assertions; identifying and mapping a set of one or more RTL lines corresponding to each filtered assertion of the filtered set of assertions; identifying and mapping individual RTL lines corresponding to each of the filtered assertion of the filtered set of assertions; and prioritising each of the mapped RTL line, thereby localising a buggy RTL line.