Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Abstract: The present invention relates to a method, system, and computer program product for performing a computer program analysis. The computer program includes a plurality of instructions. The method performs a static analysis of the computer program to compute the states of a stack pointer (SP), a frame pointer (FP), and a link register (LR) at one or more instructions of the program. The static analysis is preferably performed at compile time. Further, the method computes the states of the SP, the FP, and the LR at the instructions as determined by a dynamic analysis, wherein the dynamic analysis is preferably modeled (performed) during the static analysis. Furthermore, the states determined by the static analysis and the dynamic analysis are compared. If a discrepancy is found between the two states, metadata (information operators) is inserted into the program.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving subsets of instructions corresponding to different portions of a program, each subset assigned to one of the computation units; scheduling instructions in a given subset for execution on the assigned computation unit, including scheduling communication instructions that send to or receive from a different computation unit over the interconnection network; allocating registers in a given computation unit for storing values accessed by instructions in a subset assigned to the given computation unit; and scheduling instructions after allocating registers to account for spills of values stored in allocated register to memory, preserving the order of communication instructions scheduled before allocating registers.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving an initial partitioning of instructions into initial subsets corresponding to different portions of a program; forming a refined partitioning of the instructions into refined subsets each including one or more of the initial subsets, including determining whether to combine a first subset and a second subset to form a third subset according to a comparison of a communication cost between the first subset and second subset and a load cost of the third subset that is based at least in part on a number of instructions issued per cycle by a computation unit; and assigning each refined subset of instructions to one of the computation units for execution on the assigned computation unit.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; forming one or more memory analysis regions that include one or more of the subsets of instructions, where each subset of instructions is included in a single memory analysis region; analyzing each memory analysis region to partition memory objects and instructions that access the memory objects into equivalence classes such that instructions within an equivalence class only access objects in the same equivalence class; and assigning memory access instructions a given equivalence class to one of the computation units for execution on the assigned computation unit.

Abstract: A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable to receive a shift mask signal and a shift signal and to identify a shifting register queue within the register file based on the shift mask signal. The shifting register queue comprises a plurality of queue registers. The register file is further operable to shift the contents of the queue registers based on the shift signal.

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Abstract: A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable to receive a shift mask signal and a shift signal and to identify a shifting register queue within the register file based on the shift mask signal. The shifting register queue comprises a plurality of queue registers. The register file is further operable to shift the contents of the queue registers based on the shift signal.

Abstract: The procedure of the invention eliminates redundant conditional branch statements (CBSs) from a program, wherein the program includes (i) plural blocks of program statements, (ii) a definition statement (DEF) for each variable in the program that assigns a value to each variable, (iii) a defining point (DEFP) which is a first point in the program that a value is calculated, and (iv) plural CBSs. Each CBS transfers control to one of two target blocks of program statements, dependent upon an operation code and controlling variable that form a part of the test associated with the CBS. The procedure associates all DEFs which define a same value, with a DEFP for the same value and determines (i) a controlling variable upon which a test CBS is dependent, (ii) a DEF of the controlling variable of the test CBS and (iii) a DEFP for the DEF of the controlling variable.