Abstract: A method being implemented via execution of computing instructions configured to run at one or more processors. The method can include determining a primary store and one or more secondary stores for pickup of an order of a user, which can include: performing a first lookup call to a first cache of one or more proximate access points based on the primary store; and when a list of the one or more proximate access points is not retrieved in the first lookup call: performing a second lookup call to a second cache of active access points; determining the one or more proximate access points from among the active access points; and storing the one or more proximate access points in the first cache to update the first cache. The method also can include transmitting, for display to the user, a list of available time slots based on availability of time slots at the primary store and the one or more secondary stores. Other embodiments are described.

Abstract: A method being implemented via execution of computing instructions configured to run at one or more processors. The method can include determining a primary store and one or more secondary stores for pickup of an order of a user, based at least in part on a pickup type of the order. The method also can include determining real-time availabilities of first time slots at the primary store and real-time availabilities of second time slots at the one or more secondary stores. The method additionally can include generating a list of available time slots comprising at least a portion of the first time slots at the primary store and at least a portion of the second time slots at the one or more secondary stores, based at least in part on the real-time availabilities of the first time slots at the primary store and the real-time availabilities of the second time slots at the one or more secondary stores.

Abstract: A method including facilitating display of a first user interface to a controller. The first user interface can include fields that allow the controller to specify customizable parameters for shaping demand. The acts also can include receiving the customizable parameters from the controller. The acts additionally can include generating a historic utilization ranking corresponding to pickup time slots. The acts further can include determining in real-time a respective current utilization of each respective time slot of the pickup time slots. The acts additionally can include assigning the each respective time slot to a respective usage tier of usage tiers based at least in part on (1) a respective rank of the historic utilization ranking for the each respective time slot, (2) the respective current utilization of the each respective time slot, and (3) the customizable parameters. The acts further can include facilitating display of a second user interface to a customer.

Abstract: A method being implemented via execution of computing instructions configured to run at one or more processors. The method can include determining a primary store and one or more secondary stores for pickup of an order of a user, based at least in part on a pickup type of the order. The method also can include determining real-time availabilities of first time slots at the primary store and real-time availabilities of second time slots at the one or more secondary stores. The method additionally can include generating a list of available time slots comprising at least a portion of the first time slots at the primary store and at least a portion of the second time slots at the one or more secondary stores, based at least in part on the real-time availabilities of the first time slots at the primary store and the real-time availabilities of the second time slots at the one or more secondary stores.

Abstract: Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Iread based on the local Monte Carlo simulations around process corner G, extrapolating the worst case Iread from the normal probability distribution of Iread to define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner.

Abstract: According to one exemplary embodiment, a method for robust statistical semiconductor device modeling includes building a semiconductor device model using at least one new device parameter variation, constructing a variation library for the semiconductor device model, and verifying the variation library against measured data from physical semiconductor devices. The variation library is constructed by determining variations of the at least one new device parameter variation and standard device parameters as functions of, for example. sizes and locations of semiconductor devices on semiconductor dies.

Abstract: Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Iread based on the local Monte Carlo simulations around process corner G, extrapolating the worst case Iread from the normal probability distribution of Iread to define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner.

Abstract: The present method is a method of modeling Drain-Induced Barrier Lowering (DIBL) in a transistor model, the transistor model being based on a MOSFET transistor. The transistor model includes a base, a source, a drain, a gate, and a gate terminal. In the present method, a voltage is applied to the gate terminal, a voltage is applied to the drain, and an electrical potential is applied between the gate terminal and gate. The magnitude of electrical potential applied between the gate terminal and gate is varied in proportion to the magnitude of voltage applied to the drain.

Abstract: A method of modeling an SRAM cell is provided. Initially, transistor models are provided based on transistor devices, and an SRAM cell model is provided including the transistor models. The present methodology streamlines the modeling process by modeling in order the pull up, pass gate and pull down transistors so as to minimize the number of transistor modeling iterations needed, and by focusing on the specific areas of transistor operation to achieve the desired level of operational accuracy. Variations to the model are provided, mimicking variations in data from actual devices, and yield based on failure estimation is measured using the model and its variations.

Abstract: According to one exemplary embodiment, a method for robust statistical semiconductor device modeling includes building a semiconductor device model using at least one new device parameter variation, constructing a variation library for the semiconductor device model, and verifying the variation library against measured data from physical semiconductor devices. The variation library is constructed by determining variations of the at least one new device parameter variation and standard device parameters as functions of, for example, sizes and locations of semiconductor devices on semiconductor dies.