Abstract: A multi-phase constant-on-time (COT) system includes a first point-of-load converter configured to provide a first current and a second point-of-load converter configured to provide a second current, and a bus configured to exchange information between the first point-of-load converter and the second point-of-load converter.

Abstract: A system may include a voltage regulator controller and a driver. The voltage regulator controller may be configured to maintain a phase voltage. The driver may be associated with the phase voltage. The driver may include a first signal line that may be communicatively coupled to the voltage regulator controller. The driver may be configured to transmit a multiplexed signal on the first signal line to the voltage regulator controller.

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output voltage with controlled ripple current. The buck converter may include one or more main buck converter stages and one or more suppression buck converter stages coupled with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents to reduce ripple currents generated in the one or main buck converter stages.

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output DC voltage with controlled ripple current. The buck converter may include one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages. Each of the one or more main buck converter stages and each of the one or more suppression buck converter stages may include a stacked transistor pair with an inductor at an output. A drain terminal of one transistor of each transistor pair in the one or more main buck converter stages may be biased at a first supply voltage.

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output DC voltage with controlled ripple current. The buck converter may include one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages. Each of the one or more main buck converter stages and each of the one or more suppression buck converter stages may include a stacked transistor pair with an inductor at an output. A drain terminal of one transistor of each transistor pair in the one or more main buck converter stages may be biased at a first supply voltage.

Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

Abstract: A boost switching regulator incorporates a peak inductor current modulation circuit to modulate the peak inductor current as a function of the load current, the input voltage, the regulated output voltage, and a fixed current value. In this manner, the switching frequency of the boost regulator can be maintained above a given value or within a given frequency range over a wide range of load conditions and also over input voltage variations and output voltage settings.

Abstract: A boost switching regulator incorporates a ripple injection circuit to generate a voltage ripple signal for feedback control that mimics the actual ripple signal of the regulated output voltage. In this manner, the ripple injection circuit achieves optimal ripple injection for stable and enhanced feedback control. In one embodiment, the injected ripple signal is generated from a current injection signal that mimics the difference between the inductor current that flows through the synchronous rectifier and the load current when the synchronous rectifier is on. The injected voltage ripple signal is generated when the current injection signal is integrated by a feedforward capacitor.

Abstract: A control circuit in a PFM/PWM boost switching regulator includes a timer based PFM exit control circuit configured to receive a first control signal for controlling a main power switch, a zero-cross signal indicative of an inductor current having reached zero current value, and a timer reference signal indicative of a timer threshold duration. The timer based PFM exit control circuit assesses an idle time of the inductor current based on the first control signal and the zero-cross signal. The timer based PFM exit control circuit asserts the PFM exit signal in response to the idle time decreasing below a level being equal to or less than the timer threshold duration, and the boost switching regulator transitions out of the PFM mode and into the PWM mode in response to the PFM exit signal being asserted.

Abstract: A control circuit in a PFM/PWM boost switching regulator includes a timer based PFM exit control circuit configured to receive a first control signal for controlling a main power switch, a zero-cross signal indicative of an inductor current having reached zero current value, and a timer reference signal indicative of a timer threshold duration. The timer based PFM exit control circuit assesses an idle time of the inductor current based on the first control signal and the zero-cross signal where the idle time is the time period when the inductor current has the zero current value. The timer based PFM exit control circuit asserts the PFM exit signal in response to the idle time being equal to or less than the timer threshold duration, and the boost switching regulator transitions out of the PFM mode and into the PWM mode in response to the PFM exit signal being asserted.

Abstract: A boost switching regulator incorporates a ripple injection circuit to generate a voltage ripple signal for feedback control that mimics the actual ripple signal of the regulated output voltage. In this manner, the ripple injection circuit achieves optimal ripple injection for stable and enhanced feedback control. In one embodiment, the injected ripple signal is generated from a current injection signal that mimics the difference between the inductor current that flows through the synchronous rectifier and the load current when the synchronous rectifier is on. The injected voltage ripple signal is generated when the current injection signal is integrated by a feedforward capacitor.

Abstract: A boost switching regulator incorporates a peak inductor current modulation circuit to modulate the peak inductor current as a function of the load current, the input voltage, the regulated output voltage, and a fixed current value. In this manner, the switching frequency of the boost regulator can be maintained above a given value or within a given frequency range over a wide range of load conditions and also over input voltage variations and output voltage settings.

Abstract: A method includes receiving an input voltage at a voltage regulator and generating an output voltage using the voltage regulator, which includes an inductor. The method also includes controlling a current through the inductor using a current limit reference and modulating the current limit reference based on the input voltage and the output voltage. Modulating the current limit reference could include modulating a reference current based on a product of first and second input currents. The first input current may be based on the output voltage, and the second input current may be based on a difference between the output and input voltages. The voltage regulator may operate in a pulse frequency mode associated with a repetition rate. The repetition rate and a percentage ripple associated with the output voltage may be substantially constant over variations in the input voltage and variations in the output voltage.

Abstract: Step dimming of a fluorescent lamp load through sensing of power line interruptions generated through the toggling of a switch. The number of power line interruptions through toggling produced within a predetermined period of time identifies the level of dimming desired. In the event that interruption of power to the ballast exceeds the predetermined period of time, the lamp load will be reset to a prefixed level of illumination once power is restored.

Abstract: A low-power CMOS driver circuit capable of operating at high frequencies includes a CMOS output driver circuit and a pair of CMOS predriver circuits for driving the CMOS output driver circuit. A timing circuit is provided for generating three different timing signals for switching the predriver circuits in such a manner that the CMOS driver circuit is capable of operating at frequencies above 1 MHz without dissipating significant power.