Patents by Inventor Vinith BEJUGAM
Vinith BEJUGAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12708014Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. A first build-up layer is on at least the first surface. In some embodiments, the corner region comprises a recess and a dielectric material within the recess. In other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. The second region comprises a second compressive stress. The first compressive stress is greater than the second compressive stress.Type: GrantFiled: September 30, 2022Date of Patent: August 11, 2026Assignee: Intel CorporationInventors: Hanyu Song, Vinith Bejugam, Yonggang Li, Gang Duan, Aaron Garelick
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Publication number: 20260198337Abstract: Heterogenous through glass vias, and related packages, apparatuses, systems, and methods of fabrication are discussed. A glass substrate of a package has a first surface, an opposing second surface, and any number of first and second holes extending at partially between the first and second surfaces. Via metallizations within the first holes are heterogenous with respect to via metallizations within the second holes such that they have different lateral widths, lateral shapes, tapers, or any combination thereof.Type: ApplicationFiled: January 6, 2025Publication date: July 9, 2026Applicant: Intel CorporationInventors: Vinith Bejugam, Yonggang Li, Dhruba Pattadar, Hanyu Song, Amm Hasib, Bai Nie, Mao-Feng Tseng, Mohammad Mamunur Rahman, Srinivas Pietambaram, Samuel George, Jason Bradley, Whitney Bryks, Nevin Erturk
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Publication number: 20260090425Abstract: A package substrate includes: a sheet including glass; build-up layers respectively on a top surface and on a bottom surface of the sheet; structures defining electrically conductive pathways within the sheet and within the build-up layers; and a ribbon-shaped edge structure in recesses defined at lateral edges of the sheet and defined with respect to lateral edges of the build-up layers, the ribbon-shaped edge structure extending in a direction along a thickness of the sheet, having a lateral edge surface facing away from the sheet, and comprising an edge structure material not including glass and not including metal.Type: ApplicationFiled: September 24, 2024Publication date: March 26, 2026Applicant: Intel CorporationInventors: Zheng Kang, Anqi Zhang, Yi Li, Gang Duan, Tchefor T. Ndukum, Vinith Bejugam, Jesse Jones, Srinivas Venkata Ramanuja Pietambaram, Dhruba Kumar Pattadar, Jason Bradley, AMM Golam Hasib
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Patent number: 12354931Abstract: The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.Type: GrantFiled: May 6, 2022Date of Patent: July 8, 2025Assignee: Intel CorporationInventors: Vinith Bejugam, Kristof Darmawikarta, Yonggang Li, Samuel George, Srinivas Pietambaram
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Publication number: 20250218955Abstract: Microelectronic integrated circuit package structures include an apparatus having a a glass substrate embedded within a package substrate. The glass substrate comprises one or more trenches extending within a first portion, the one or more trenches comprising a first conductive layer on individual trench sidewalls, a dielectric layer on the first conductive layer and a second conductive layer on the dielectric layer. A second portion of the glass substrate is below the first portion.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Brandon Marin, Srinivas Pietambaram, Gang Duan, Joshua Stacey, Mahdi Mohammadighaleni, Whitney Bryks, Wendy Lin, Dilan Seneviratne, Vinith Bejugam, Dhruba Pattadar
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Publication number: 20250183182Abstract: Various techniques for alleviating (e.g., mitigating or reducing) stresses between glass core materials and electrically conductive materials deposited in through-glass vias (TGVs) and related devices and methods are disclosed. In one aspect, a microelectronic assembly includes a glass core having a first face and a second face opposite the first face, and a TGV extending through the glass core between the first face and the second face, wherein the TGV includes a conductive material and a buffer layer between the conductive material and the glass core, wherein a CTE of the buffer layer is smaller than a CTE of the conductive material.Type: ApplicationFiled: November 30, 2023Publication date: June 5, 2025Inventors: Bohan Shan, Mahdi Mohammadighaleni, Joshua Stacey, Ehsan Zamani, Aaditya Candadai, Jacob Vehonsky, Daniel Wandera, Mitchell Page, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jeremy Ecton, Brandon C. Marin, Onur Ozkan, Vinith Bejugam, Dhruba Pattadar, Amm Hasib, Nicholas Haehn, Makoyi Watson, Sanjay Tharmarajah, Jason M. Gamba, Yuqin Li, Astitva Tripathi, Mohammad Mamunur Rahman, Haifa Hariri, Shayan Kaviani, Logan Myers, Darko Grujicic, Elham Tavakoli, Whitney Bryks, Dilan Seneviratne, Bainye Angoua, Peumie Abeyratne Kuragama, Hongxia Feng, Kyle Jordan Arrington, Bai Nie, Jose Waimin, Ryan Carrazzone, Haobo Chen, Dingying Xu, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Bin Mu, Thomas S. Heaton, Rahul N. Manepalli
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Publication number: 20240217216Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Inventors: Kristof DARMAWIKARTA, Tarek A. IBRAHIM, Srinivas V. PIETAMBARAM, Dilan SENEVIRATNE, Jieying KONG, Thomas HEATON, Whitney BRYKS, Vinith BEJUGAM, Junxin WANG, Gang DUAN
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Publication number: 20240213328Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a via opening through the core. In an embodiment, the via opening comprises sidewalls. In an embodiment, a composite layer is provided along the sidewalls, and the composite layer comprises carbon. In an embodiment, the package substrate further comprises a via within the via opening, where the via is electrically conductive.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Inventors: Vinith BEJUGAM, Yonggang LI, Srinivas V. PIETAMBARAM, Chandrasekharan NAIR, Whitney BRYKS, Gene CORYELL
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Publication number: 20240215163Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprise glass. In an embodiment, a via is provided through the substrate, where the via is electrically conductive. In an embodiment, a recess is formed into the first surface of the substrate, and a trace is embedded in the recess. In an embodiment, the trace is electrically conductive.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Inventors: Onur OZKAN, Jacob VEHONSKY, Vinith BEJUGAM, Nicholas S. HAEHN, Andrea NICOLAS FLORES, Mao-Feng TSENG
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Publication number: 20240188225Abstract: A method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.Type: ApplicationFiled: December 1, 2022Publication date: June 6, 2024Inventors: Vinith BEJUGAM, Rengarajan SHANMUGAM, Srinivas PIETAMBARAM, Mao-Feng TSENG, Yonggang LI
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Publication number: 20240178157Abstract: Embodiments disclosed herein include package substrates. In a particular embodiment, the package substrate comprises a core. The core may be a glass core. In an embodiment, buildup layers are provided over the core, and a shape memory polymer (SMP) is provided over the core.Type: ApplicationFiled: November 29, 2022Publication date: May 30, 2024Inventors: Vinith BEJUGAM, Whitney BRYKS, Brandon C. MARIN, Vishal Bhimrao ZADE, Deniz TURAN, Srinivas V. PIETAMBARAM
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Publication number: 20240112970Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. A first build-up layer is on at least the first surface. In some embodiments, the corner region comprises a recess and a dielectric material within the recess. In other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. The second region comprises a second compressive stress. The first compressive stress is greater than the second compressive stress.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Hanyu Song, Vinith Bejugam, Yonggang Li, Gang Duan, Aaron Garelick
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Publication number: 20240079530Abstract: Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Jacob VEHONSKY, Onur OZKAN, Vinith BEJUGAM, Mao-Feng TSENG, Nicholas HAEHN, Andrea NICOLAS FLORES, Ali LEHAF, Benjamin DUONG, Joshua STACEY
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Publication number: 20240079259Abstract: The present disclosure is directed to a system that uses a dual surface substrate carrier that includes a first transparent support with a first top surface and first bottom surface, a second transparent support with a second top surface and second bottom surface, and a reflective film positioned between and attached to the first transparent support and the second transparent support. The first transparent support has a first set of trenches configured in the first top surface that form a first set of ridges between the plurality of trenches and the second transparent support has a second set of trenches configured in the second top surface that form a second set of ridges between the plurality of trenches. The first transparent support is also configured with a first build surface and the second transparent support is also configured with a second build surface that are platforms for building package substrates.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Inventors: Jacob VEHONSKY, Onur OZKAN, Vinith BEJUGAM, Mao-Feng TSENG, Andrea NICOLAS, Nicholas HAEHN
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Publication number: 20230361002Abstract: The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Inventors: Vinith BEJUGAM, Kristof DARMAWIKARTA, Yonggang LI, Samuel GEORGE, Srinivas PIETAMBARAM
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Publication number: 20230313383Abstract: A method for electrolessly depositing a metal layer onto a substrate, including the following chronological steps: a) treating the substrate surface to be plated with an etching solution; b) treating the substrate surface to be plated with a polyelectrolyte or an organosilane compound; c) treating the surface to be plated with a solution containing metal particles; d) treating the surface to be plated with a solution containing at least one salt of the metal to be deposited onto the substrate.Type: ApplicationFiled: August 23, 2021Publication date: October 5, 2023Inventors: Vinith Bejugam, Thorsten Teutsch
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Publication number: 20230294204Abstract: A method includes forming a solvent on a stage, and placing, on the solvent formed on the stage, a bottom surface of a substrate on which a residue is formed, so that the residue moves away from the bottom surface of the substrate into the solvent. The method further includes removing the substrate from the solvent into which the residue is moved.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventors: Jeremy ECTON, Vinith BEJUGAM, Jefferson KAPLAN, Yonggang LI, Whitney BRYKS, Samuel GEORGE, Jeremy CROSS