Abstract: A process for reverse isomerization of a light naphtha feedstock containing branched C5-C7 paraffins. The process includes feeding a mixed feed stream including the light naphtha feedstock to a separation unit to generate an iso-paraffin stream and one or more normal paraffin streams. The process further includes mixing hydrogen gas and a hydrocarbon feed stream containing the iso-paraffin stream to form a hydrogen-enriched liquid feed stream which is provided to a reverse isomerization reactor. The hydrogen-enriched liquid feed stream is contacted with a solid reverse isomerization catalyst for reverse hydroisomerization in a substantially two-phase liquid-solid reverse isomerization fixed-bed reaction zone convert iso-paraffins to normal paraffins. The isomerization effluent stream is provided to a stabilization column to generate a stabilized isomerate stream which is combined with the light naphtha feedstock to generate the mixed feed stream.

Abstract: A system includes sensors, a first memory component, a second memory component, and an interface. The sensors are configured to generate data responsive to stimuli. Each sensor may transmit its associated data as it becomes available. The first memory component may receive and store sensor data. The second memory component may receive data from the first memory component. The interface may receive data from the second memory component. The sensor data generated during a time which the interface is receiving data from the second memory component is transmitted to the first memory component and stored thereto. No data is transmitted from the first memory component or from the sensors to the second memory component during the time which the interface is receiving data from the second memory component. Subsequently, a subset of data stored on the first memory component is advanced to the second memory component.

Abstract: A system includes sensors, a first memory component, a second memory component, and an interface. The sensors are configured to generate data responsive to stimuli. Each sensor may transmit its associated data as it becomes available. The first memory component may receive and store sensor data. The second memory component may receive data from the first memory component. The interface may receive data from the second memory component. The sensor data generated during a time which the interface is receiving data from the second memory component is transmitted to the first memory component and stored thereto. No data is transmitted from the first memory component or from the sensors to the second memory component during the time which the interface is receiving data from the second memory component. Subsequently, a subset of data stored on the first memory component is advanced to the second memory component.

Abstract: A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion. The first portion is allocated to storing instructions for execution by the one or more processors. The second portion is allocated to storing data generated by the one or more processor, and the third portion is allocated to storing data from the one or more sensors. The third portion being a first-in-first-out (FIFO) having one or more FIFO portions, The device further includes a control logic operable to allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors. The size each of the FIFO portions depends on the bandwidth of the sensors and the number of sensors.

Abstract: A device and method for managing external sensors are disclosed. The device comprises at least one embedded processor and a memory device and at least one bus controller that can be used by the embedded processors to communicate with external sensors. The embedded processor includes a mechanism to receive a control input to retrieve raw data from at least one sensor external to the device. The embedded processors may include another mechanism to receive a control input interrupting the embedded processors at regular intervals of time to retrieve raw data from at least one sensor external to the device.

Abstract: A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion. The first portion is allocated to storing instructions for execution by the one or more processors. The second portion is allocated to storing data generated by the one or more processor, and the third portion is allocated to storing data from the one or more sensors. The third portion being a first-in-first-out (FIFO) having one or more FIFO portions, The device further includes a control logic operable to allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors. The size each of the FIFO portions depends on the bandwidth of the sensors and the number of sensors.