Abstract: The present invention relates to a method of printing a print job by an image reproduction system. The print job specifies a printing step on an image receiving medium and a finishing step in or on the image receiving medium. The method comprises the steps of receiving the print job by the image reproduction system and receiving a trigger by a controller of the image reproduction system that the finishing step is not to be performed. In such a case for a digital image comprised in print job data of the print job, at least one digital finishing visualization image of a predetermined visual appearance of a result of the finishing step in or on the image receiving medium is obtained as well as a position of the digital image for merging the obtained at least one digital finishing visualization image with the digital image. The digital image is updated by merging the obtained at least one digital finishing visualization image with the digital image at the obtained position.

Abstract: A printing system comprising a controller for controlling the processing of print jobs, a plurality of input holders for holding print media to be printed upon, a print engine for disposing marking material on the print media, and a plurality of output holders for holding the print media when the marking material has been disposed on the print media by the print engine and the print media is ready for taking out by an operator. The controller is configured to establish and to maintain a plurality of physical configurations of the printing system. Each physical configuration comprises the print engine, at least one input holder out of the plurality of input holders and at least one output holder out of the plurality of output holders.

Abstract: The present invention relates to a method of printing a print job by an image reproduction system. The print job specifies a printing step on an image receiving medium and a finishing step in or on the image receiving medium. The method comprises the steps of receiving the print job by the image reproduction system and receiving a trigger by a controller of the image reproduction system that the finishing step is not to be performed. In such a case for a digital image comprised in print job data of the print job, at least one digital finishing visualization image of a predetermined visual appearance of a result of the finishing step in or on the image receiving medium is obtained as well as a position of the digital image for merging the obtained at least one digital finishing visualization image with the digital image. The digital image is updated by merging the obtained at least one digital finishing visualization image with the digital image at the obtained position.

Abstract: A memory circuit includes at least one bit cell that receives a word line, complementary bit lines and an array supply voltage and a word line suppression circuit. The word line suppression circuit includes two PFETs with their drains connected to the word line and their sources connected to the array supply voltage and an NFET with its source connected to ground and its drain connected to the word line. The NFET is inactivated before the PFETs are activated. One of the PFETs is activated before the other PFET is activated so as to control the slew rate of the word line and improve the static noise margin of the at least one bit cell.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving the array supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a first switch coupled in series and a second switch. The switches are responsive to a control signal. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: An integrated circuit (IC). The integrated circuit comprises an array (14) of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (40), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry (12) for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry (12) for reading selected ones of the data cells in a read mode.

Abstract: An integrated circuit (IC). The integrated circuit comprises an array (14) of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (40), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry (12) for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry (12) for reading selected ones of the data cells in a read mode.

Abstract: A circuit for charging or discharging a capacitive load. The circuit includes a buffer driver comprising first and second input terminals and an output terminal, and a reference voltage generator coupled to the buffer driver. The reference voltage generator includes an enablement signal terminal, first and second reference voltage terminals, and a circuit operable to provide first and second reference voltages at the first and second reference voltage terminals in response to a first signal at the enablement terminal. The reference voltage generator also provides first and second rail voltages in response to a second signal at the enablement terminal.

Abstract: In a DRAM unit in which the substrate bias voltage is maintained within predetermined limits by a of voltage detectors and a charge pump, a third voltage detector is provided which detects a intermediate substrate bias voltage level that is within the voltage range identified by the pair of voltage detectors. When the third voltage level detects that the intermediate substrate bias voltage has been traversed, the charge pump is activated at a reduced level to drive the substrate bias voltage to recross the intermediate substrate bias voltage level. This technique permits the DRAM unit to operate in a stand-by mode at a lower power level, especially in a standby mode of operation, than when the substrate bias voltage is maintained only by the two voltage limit detectors and a single power level charge pump.