Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

Abstract: Techniques are provided for assessing and determining risks that are posed by various users to a website. The determined risk for each user can be used to modify the user experience of the website in a manner that is commensurate with the risk (or non-risk) posed by the user. Assessment of risks posed a website guest can be performed by collecting guest-related data from a plurality of different service engines, aggregating contextual information from the guest-related data, and calculating a risk score based on the contextual information. The risk score can represent the internal reputation of the guest using the guest device. The risk score can be transmitted to a remote computing device and used to modify content of the website according to the risk score. Further, a recommended action can be determined based on the risk score, which can be taken by a backend service for the website guest.

Abstract: Methods, systems, and computer readable media for actively diagnosing and remediating performance degradation in a production network. An example system includes at least one event correlation engine configured for identifying a performance degradation event in the production network; correlating network log and event data with the performance degradation event; and storing at least some of the network log and event data for simulating the performance degradation event. The system includes a remediation engine configured for determining a production network remediation plan and determining a test plan for the production network remediation plan. The system includes at least one network simulation engine configured for simulating the production network using the stored at least some of the network log and event data and the production network remediation plan; executing the test plan; and generating a test result for the production network remediation plan based on executing the test plan.

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

Abstract: In a memory device, a static random access memory (SRAM) circuit includes an array of SRAM cells arranged in rows and columns and configured to store data. The SRAM array is configured to: store a first set of information for a machine learning (ML) process in a lookup table in the SRAM array; and consecutively access, from the lookup table, information from a selected set of the SRAM cells along a row of the SRAM cells. A memory controller circuit is configured to select the set of the SRAM cells based on a second set of information for the ML process.

Abstract: In an example, an apparatus includes a level-shifting circuit and a ramp detector. The level-shifting circuit has a current choke and a transistor coupled across the current choke, the level-shifting circuit adapted to be coupled to a first voltage source. The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, the ramp detector adapted to be coupled to a second voltage source.

Abstract: In an example, an apparatus includes a level-shifting circuit and a ramp detector. The level-shifting circuit has a current choke and a transistor coupled across the current choke, the level-shifting circuit adapted to be coupled to a first voltage source. The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, the ramp detector adapted to be coupled to a second voltage source.

Abstract: An electronic device having multiple power output circuits that individually include a switch control input, a bypass control input, an output transistor and an output control circuit that includes an RC circuit with a resistor and a capacitor coupled to the output transistor gate and a bypass switch in parallel with the RC circuit resistor. The electronic device includes a controller that selects one of the power output circuits for a given power transfer cycle, closes the bypass switch to bypass the resistor of the selected power output circuit and turns the output transistor of the selected power output circuit on to transfer current from the inductor to a load of the selected power output circuit.

Abstract: Techniques are provided for assessing and determining risks that are posed by various users to a website. The determined risk for each user can be used to modify the user experience of the website in a manner that is commensurate with the risk (or non-risk) posed by the user. Assessment of risks posed a website guest can be performed by collecting guest-related data from a plurality of different service engines, aggregating contextual information from the guest-related data, and calculating a risk score based on the contextual information. The risk score can represent the internal reputation of the guest using the guest device. The risk score can be transmitted to a remote computing device and used to modify content of the website according to the risk score. Further, a recommended action can be determined based on the risk score, which can be taken by a backend service for the website guest.

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

Abstract: According to one method for debugging test traffic generation, the method occurs at a test system implemented using at least one processor and at least one memory. The method includes generating test traffic, wherein generating the test traffic includes receiving routing information from a system under test (SUT) via at least one routing protocol, determining traffic header data using the routing information, and storing resolution processing path information indicating how the traffic header data was determined; and displaying, using a display, test traffic data, wherein displaying the test traffic data includes displaying at least some of the resolution processing path information for at least some of the traffic header data.

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.

Abstract: Methods, systems, and computer readable media for network traffic statistics collection are disclosed. One method for network traffic statistics collection includes during testing of a system under test (SUT): receiving a first trigger message indicating a first message group context for statistics collection; receiving, from the SUT, a first test message of a plurality of test messages, wherein the first test message includes a first message group identifier (MGID) and a second MGID, wherein the first MGID is associated with the first message group context and the second MGID is associated with a second message group context; and performing, using the first MGID, statistics collection associated with the first message group context. The method may also include changing from the first message group context to the second message group context during the test and using the second message group context for statistics collection.

Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.

Abstract: A system includes a test controller configured for testing a device under test (DUT). Testing the DUT includes creating a link aggregation group (LAG) with the DUT, and the LAG includes a first link and a second link. The system includes a first traffic generator circuit including a first physical network port and a first port processor configured to transmit a first stream of test packets over the first link of the LAG. The system includes a second traffic generator circuit including a second physical network port and a second port processor configured to transmit a second stream of test packets over the second link of the LAG. The system is configured for instructing the first port processor to transmit both the first stream of test packets and the second stream of test packets on the first physical network port in response to detecting an anomaly on the second link.

Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.

Abstract: A system includes a test controller configured for testing a device under test (DUT). Testing the DUT includes creating a link aggregation group (LAG) with the DUT, and the LAG includes a first link and a second link. The system includes a first traffic generator circuit including a first physical network port and a first port processor configured to transmit a first stream of test packets over the first link of the LAG. The system includes a second traffic generator circuit including a second physical network port and a second port processor configured to transmit a second stream of test packets over the second link of the LAG. The system is configured for instructing the first port processor to transmit both the first stream of test packets and the second stream of test packets on the first physical network port in response to detecting an anomaly on the second link.

Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.