Patents by Inventor Vinod K. Balakrishnan

Vinod K. Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for implementing a communication channel with local and global resources
    Patent number: 8117620
    Abstract: Apparatus, system, and method including a local resource to transfer information between a first processing unit and a second processing unit; and a global resource to transfer information between said first processing unit and said second processing unit, and to transfer information between said first processing unit and a third processing unit if said local resource is full are described.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: February 14, 2012
    Assignee: Intel Corporation
    Inventors: Arun Raghunath, Vinod K. Balakrishnan
  • Allocating call stack frame entries at different memory levels to functions in a program
    Patent number: 7512738
    Abstract: Provided are a method, system, and program for allocating call stack frame entries at different memory levels to functions in a program. Functions in a program accessing state information stored in call stack frame entries are processed. Call stack frame entries are allocated to the state information for each function, wherein the call stack frame entries span multiple memory levels, and wherein one function is capable of being allocated stack entries in multiple memory levels.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: Vinod K. Balakrishnan, Ruiqi Lian, Junchao Zhang, Dz-ching Ju
  • Packet processing system
    Patent number: 7379460
    Abstract: Some embodiments relate to a processor to provide a plurality of execution threads, a local memory associated with the processor, and a content-addressable memory associated with the processor. An execution thread of the processor may determine an ordering queue, associate a current thread with a last position in the ordering queue, receive a queue release signal from a previous thread in the ordering queue, and execute a critical code segment associated with the ordering queue.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventor: Vinod K. Balakrishnan
  • Packet processing system
    Publication number: 20040246980
    Abstract: Some embodiments relate to a processor to provide a plurality of execution threads, a local memory associated with the processor, and a content-addressable memory associated with the processor. An execution thread of the processor may determine an ordering queue, associate a current thread with a last position in the ordering queue, receive a queue release signal from a previous thread in the ordering queue, and execute a critical code segment associated with the ordering queue.
    Type: Application
    Filed: June 6, 2003
    Publication date: December 9, 2004
    Inventor: Vinod K. Balakrishnan