Patents by Inventor Vinod K. Grover
Vinod K. Grover has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190278593Abstract: Systems and methods for obtaining a set of instructions for executing a computer program and generating executable code for the computer program based, at least in part, on scheduling operations associated with the executable code according to a polyhedral representation of a directed acyclic graph. The set of instructions may be represented as a domain-specific language. The executable code may be executable code for a specific processor architecture.Type: ApplicationFiled: February 15, 2019Publication date: September 12, 2019Inventors: Venmugil Elango, Norman Rubin, Mahesh Ravishankar, Vinod K. Grover
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Patent number: 9658880Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.Type: GrantFiled: March 18, 2013Date of Patent: May 23, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Jan Gray, Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod K. Grover, Michael Magruder, Gad Sheaffer
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Patent number: 9411635Abstract: Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. Multiple closed nested transactions are created for a single parent transaction, and the closed nested transactions are executed concurrently as parallel nested transactions. Various techniques are used to ensure effects of the parallel nested transactions are hidden from other transactions outside the parent transaction until the parent transaction commits. For example, retry is allowed to work correctly with parallel nested transactions. When a transaction that is a parallel nested transaction or a child transaction of the parallel nested transaction executes a retry, a read set of the transaction is registered for the retry. When a decision is made to propagate the retry past a parallel nested transaction parent of the transaction, keeping the read set registered and making the read set part of a parent read set.Type: GrantFiled: September 18, 2012Date of Patent: August 9, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Michael M. Magruder, David Detlefs, John J. Duffy, Goetz Graefe, Vinod K. Grover
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Patent number: 9047139Abstract: Software transactional memory (STM) primitives are provided that allow the results of prior open calls to be used by subsequent open calls either as-is or through another STM primitive that consumes the results of the previous invocation. The STM primitives are configured to ensure that the address of a shadow copy representing a memory location will not changed across a wide range of operations and thereby enable re-use of the shadow copy.Type: GrantFiled: June 27, 2008Date of Patent: June 2, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Yosseff Levanoni, David L. Detlefs, Michael M. Magruder, Vinod K. Grover
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Patent number: 8839213Abstract: A compiler is provided that determines when the use of software transactional memory (STM) primitives may be optimized with respect to a set of collectively dominating STM primitives. The compiler analysis coordinates the use of variables containing possible shadow copy pointers to allow the analysis to be performed for both direct write and buffered write STM systems. The coordination of the variables containing the possible shadow copy pointers ensures that the results of STM primitives are properly reused. The compiler analysis identifies memory accesses where STM primitives may be eliminated, combined, or substituted for lower overhead STM primitives.Type: GrantFiled: June 27, 2008Date of Patent: September 16, 2014Assignee: Microsoft CorporationInventors: David L. Detlefs, Michael M. Magruder, Yosseff Levanoni, Vinod K. Grover
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Publication number: 20130238579Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.Type: ApplicationFiled: March 18, 2013Publication date: September 12, 2013Applicant: Microsoft CorporationInventors: Jan Gray, Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod K. Grover, Michael Magruder, Gad Sheaffer
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Patent number: 8402218Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction.Type: GrantFiled: December 15, 2009Date of Patent: March 19, 2013Assignee: Microsoft CorporationInventors: Jan Gray, Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod K. Grover, Michael Magruder, Gad Sheaffer
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Patent number: 8341133Abstract: A software transactional memory system is provided that generates and stores compressed transactional locks in a portion of object headers. The software transactional memory system allocates preferred write log memory with a predefined size of memory that corresponds to a number of bits in the compressed transactional locks. The compressed transactional locks identify write log entries in corresponding write logs in the preferred write log memory. If the preferred write log memory becomes full, additional write log memory is allocated for write log entries and subsequent transactional locks are stored uncompressed in an auxiliary memory. A pointer that may be used to locate the uncompressed transactional lock is stored in the header. If an object header with a compressed transactional lock is needed for another use, the compressed transactional lock is uncompressed and stored in the auxiliary memory. A pointer that may be used to locate the uncompressed transactional lock is stored in the header.Type: GrantFiled: June 27, 2008Date of Patent: December 25, 2012Assignee: Microsoft CorporationInventors: David L. Detlefs, Vinod K. Grover, Yosseff Levanoni, Michael M. Magruder
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Patent number: 8271464Abstract: Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. Releasing a duplicate write lock for rollback is supported. During rollback processing of a parallel nested transaction, a write log entry is encountered that represents a write lock. If the write lock is a duplicate, a global lock is used to synchronize access to a global versioned write lock map. Optimistic read validation is supported. During validation, if a versioned write lock indicates a sibling conflict, consult information to determine if a parallel nested transaction should be doomed. Write lock acquisition is supported. Upon attempting to acquire a write lock for a parallel nested transaction, a transactional memory word is analyzed to determine if the write lock can be obtained. If the transactional memory word indicates a versioned write lock, retrieve a write log entry pointer from a global versioned write lock map.Type: GrantFiled: October 27, 2010Date of Patent: September 18, 2012Assignee: Microsoft CorporationInventors: Michael M. Magruder, David Detlefs, John Joseph Duffy, Goetz Graefe, Vinod K. Grover
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Patent number: 8271465Abstract: Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. Multiple closed nested transactions are created for a single parent transaction, and the closed nested transactions are executed concurrently as parallel nested transactions. Various techniques are used to ensure effects of the parallel nested transactions are hidden from other transactions outside the parent transaction until the parent transaction commits. For example, versioned write locks are used with parallel nested transactions. When a transactional memory word changes from a write lock to a versioned write lock, an entry is made in a global versioned write lock map to store a pointer to a write log entry that the versioned write lock replaced. When the versioned write lock is encountered during transaction processing, the global versioned write lock map is consulted to translate the versioned write lock to the pointer to the write log entry.Type: GrantFiled: February 15, 2011Date of Patent: September 18, 2012Assignee: Microsoft CorporationInventors: Michael M. Magruder, David Detlefs, John J. Duffy, Goetz Graefe, Vinod K. Grover
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Patent number: 8112597Abstract: Typical computer programs may incur costly memory errors that result in corrupted data. A new memory model is presented wherein it may be determined that certain data is critical and critical data may be stored and protected during computer application execution. Critical Memory allows that data determined to be critical may be stored and retrieved using functions enabled to increase the reliability of the data. Critical Memory presents a memory model where a subset of memory designated as critical memory may be used to store a subset of data deemed critical data. Probabilistic guarantees of data value consistency are provided by the employment of the new memory model. The memory model and functions presented are compatible with existing third-party libraries such that third-party libraries may be compatibly called from processes using critical memory.Type: GrantFiled: December 8, 2006Date of Patent: February 7, 2012Assignee: Microsoft CorporationInventors: Karthik Pattabiraman, Vinod K. Grover, Benjamin G. Zorn
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Patent number: 8006227Abstract: Various technologies and techniques are disclosed for creating and/or locating transactional code blocks in a transactional memory system. A user such as a software developer can decorate a particular function with an identifier to indicate that the particular function is transaction-safe. A normal version and a transactional version are then created for each function of a software application that is marked as transaction-safe. A normal version is created for each function that is not marked as transaction-safe. For the normal version of each function that is marked as transaction-safe, a stub pointer in the normal version is pointed to the transactional version. The proper version of the function is then called depending on the execution context.Type: GrantFiled: June 1, 2007Date of Patent: August 23, 2011Assignee: Microsoft CorporationInventors: David Callahan, Vinod K. Grover
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Publication number: 20110145304Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: MICROSOFT CORPORATIONInventors: Jan Gray, Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod K. Grover, Michael Magruder, Gad Sheaffer
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Patent number: 7962456Abstract: Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. For example, pessimistic reads are supported. A pessimistic duplication detection data structure is created for a parallel nested transaction. An entry is made into the data structure for each pessimistic read in the parallel nested transaction. When committing the parallel nested transaction, new pessimistic read locks are passed to an immediate parent, and an entry is made into a separate pessimistic duplication detection data structure of the immediate parent with synchronization between sibling transactions. The pessimistic duplication detection data structures can also be used for upgrades from pessimistic reads to write locks. Retry operations are supported with parallel nested transactions. Write abort compensation maps can be used with parallel nested transactions to detect and handle falsely doomed parent transactions.Type: GrantFiled: September 18, 2007Date of Patent: June 14, 2011Assignee: Microsoft CorporationInventors: Michael M. Magruder, David Detlefs, John Joseph Duffy, Goetz Graefe, Vinod K. Grover
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Publication number: 20110138145Abstract: Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. Multiple closed nested transactions are created for a single parent transaction, and the closed nested transactions are executed concurrently as parallel nested transactions. Various techniques are used to ensure effects of the parallel nested transactions are hidden from other transactions outside the parent transaction until the parent transaction commits. For example, versioned write locks are used with parallel nested transactions. When a transactional memory word changes from a write lock to a versioned write lock, an entry is made in a global versioned write lock map to store a pointer to a write log entry that the versioned write lock replaced. When the versioned write lock is encountered during transaction processing, the global versioned write lock map is consulted to translate the versioned write lock to the pointer to the write log entry.Type: ApplicationFiled: February 15, 2011Publication date: June 9, 2011Applicant: Microsoft CorporationInventors: Michael M. Magruder, David Detlefs, John Joseph Duffy, Goetz Graefe, Vinod K. Grover
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Patent number: 7949841Abstract: Typical computer programs may incur costly memory errors that result in corrupted data. A new memory model is presented wherein it may be determined that certain data is critical and critical data may be stored and protected during computer application execution. Critical Memory allows that data determined to be critical may be stored and retrieved using functions enabled to increase the reliability of the data. Functions are presented enabling allocation of redundant computer memory; functions are presented enabling consistently writing critical data to redundant locations; and functions are presented enabling reading critical data while ensuring that the data read is consistent with the most recent write of critical data and enabled to repair inconsistent data. The memory model and functions presented are designed to be compatible with existing third-party libraries.Type: GrantFiled: December 8, 2006Date of Patent: May 24, 2011Assignee: Microsoft CorporationInventors: Karthik Pattabiraman, Vinod K. Grover, Benjamin G. Zorn
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Patent number: 7908255Abstract: Various technologies and techniques are disclosed that support buffered writes and enforced serialization order in a software transactional memory system. A buffered write process is provided that performs writes to shadow copies of objects and writes content back to the objects after validating a respective transaction during commit. When a write lock is first obtained for a particular transaction, a shadow copy is made of a particular object. Writes are performed to and reads from the shadow copy. After validating the particular transaction during commit, content is written from the shadow copy to the particular object. A transaction ordering process is provided that ensures that an order in which the transactions are committed matches an abstract serialization order of the transactions. Transactions are not allowed to commit until their ticket number matches a global number that tracks the next transaction that should commit.Type: GrantFiled: April 11, 2007Date of Patent: March 15, 2011Assignee: Microsoft CorporationInventors: David Detlefs, John Joseph Duffy, Michael M Magruder, Goetz Graefe, Vinod K Grover, Timothy Lawrence Harris
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Patent number: 7899999Abstract: Various technologies and techniques are disclosed for detecting falsely doomed parent transactions of nested children in transactional memory systems. When rolling back nested transactions, a release count is tracked each time that a write lock is released due to rollback for a given nested transaction. For example, a write abort compensation map can be used to track the release count for each nested transaction. The number of times the nested transactions releases a write lock is recorded in their respective write abort compensation map. The release counts can be used during a validation of a parent transaction to determine if a failed optimistic read is really valid. If an aggregated release count for the nested children transactions accounts for the difference in version numbers exactly, then the optimistic read is valid.Type: GrantFiled: June 27, 2007Date of Patent: March 1, 2011Assignee: Microsoft CorporationInventors: Michael M. Magruder, David Detlefs, John Joseph Duffy, Goetz Graefe, Vinod K. Grover
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Publication number: 20110040738Abstract: Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. Releasing a duplicate write lock for rollback is supported. During rollback processing of a parallel nested transaction, a write log entry is encountered that represents a write lock. If the write lock is a duplicate, a global lock is used to synchronize access to a global versioned write lock map. Optimistic read validation is supported. During validation, if a versioned write lock indicates a sibling conflict, consult information to determine if a parallel nested transaction should be doomed. Write lock acquisition is supported. Upon attempting to acquire a write lock for a parallel nested transaction, a transactional memory word is analyzed to determine if the write lock can be obtained. If the transactional memory word indicates a versioned write lock, retrieve a write log entry pointer from a global versioned write lock map.Type: ApplicationFiled: October 27, 2010Publication date: February 17, 2011Applicant: MICROSOFT CORPORATIONInventors: Michael M. Magruder, David Detlefs, John Joseph Duffy, Goetz Graefe, Vinod K. Grover
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Patent number: 7890472Abstract: Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. Multiple closed nested transactions are created for a single parent transaction, and the closed nested transactions are executed concurrently as parallel nested transactions. Various techniques are used to ensure effects of the parallel nested transactions are hidden from other transactions outside the parent transaction until the parent transaction commits. For example, versioned write locks are used with parallel nested transactions. When a transactional memory word changes from a write lock to a versioned write lock, an entry is made in a global versioned write lock map to store a pointer to a write log entry that the versioned write lock replaced. When the versioned write lock is encountered during transaction processing, the global versioned write lock map is consulted to translate the versioned write lock to the pointer to the write log entry.Type: GrantFiled: September 18, 2007Date of Patent: February 15, 2011Assignee: Microsoft CorporationInventors: Michael M. Magruder, David Detlefs, John Joseph Duffy, Goetz Graefe, Vinod K. Grover