Patents by Inventor Vinod K. Kathail

Vinod K. Kathail has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10891414
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele
  • Patent number: 10860766
    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 8, 2020
    Assignee: XILINX, INC.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss, Vinod K. Kathail, Ajit K. Agarwal, Ralph D. Wittig
  • Publication number: 20200371759
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Akella Sastry, Vinod K. Kathail, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddarth Rele
  • Publication number: 20200372123
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele
  • Publication number: 20200371761
    Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Samuel R. Bayliss, Vinod K. Kathail, Ralph D. Wittig, Philip B. James-Roxby, Akella Sastry
  • Publication number: 20200372200
    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss, Vinod K. Kathail, Ajit K. Agarwal, Ralph D. Wittig
  • Patent number: 10635769
    Abstract: Event tracing for a system-on-chip (SOC) may be implemented by instrumenting, using a computer, a design for the SOC with instrumentation program code that, responsive to execution by a processor of the SOC, generates software trace events. The design may be specified in a high level programming language. A circuit design specifying an accelerator circuit for a function of the design may be generated using the computer. The accelerator circuit is configured for implementation within programmable circuitry of the SOC. The circuit design may be instrumented to include trace circuitry using the computer. The trace circuitry may be configured to detect hardware trace events for operation of the accelerator circuit, receive the software trace events, and combine the hardware and software trace events into time synchronized trace data.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 28, 2020
    Assignee: Xilinx, Inc.
    Inventors: Samuel A. Skalicky, L. James Hwang, Vinod K. Kathail
  • Patent number: 9880966
    Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: January 30, 2018
    Assignee: XILINX, INC.
    Inventors: L. James Hwang, Vinod K. Kathail, Sundararajarao Mohan, Jorge E. Carrillo, Hua Sun
  • Patent number: 9805152
    Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: October 31, 2017
    Assignee: XILINX, INC.
    Inventors: Jorge E. Carrillo, Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Hua Sun
  • Patent number: 9652570
    Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 16, 2017
    Assignee: XILINX, INC.
    Inventors: Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Jorge E. Carrillo, Hua Sun, Tom Shui, Yogesh L. Chobe
  • Patent number: 9223921
    Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: December 29, 2015
    Assignee: XILINX, INC.
    Inventors: Jorge E. Carrillo, L. James Hwang, Hua Sun, Sundararajarao Mohan, Vinod K. Kathail
  • Patent number: 9147024
    Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: September 29, 2015
    Assignee: XILINX, INC.
    Inventors: Vinod K. Kathail, Hua Sun, Sundararajarao Mohan, L. James Hwang, Yogesh L. Chobe
  • Patent number: 8762916
    Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 24, 2014
    Assignee: Xilinx, Inc.
    Inventors: Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Hua Sun
  • Patent number: 7107199
    Abstract: A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert S. Schreiber, Shail Aditya Gupta, Vinod K. Kathail, Santosh George Abraham, Bantwal Ramakrishna Rau
  • Patent number: 6772106
    Abstract: An automatic and retargetable computer design system is using a combination of simulation and performance prediction to investigate a plurality of target computer systems. A high-level specification and a predetermined application are used by the computer design system to provide inputs into a computer evaluator. The computer evaluator has reference computer system dependent and independent systems for producing a reference representation and dynamic behavior information, respectively, of the application. The reference representation and information are mated to produce further information to drive a simulator. The simulator provides performance information of a reference computer system. The performance information is provided to another computer evaluator, which has a target computer system dependent system for producing a target representation of the application for the plurality of target computer systems.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: August 3, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Scott A. Mahlke, Santosh G. Abraham, Vinod K. Kathail
  • Publication number: 20040088529
    Abstract: A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventors: Robert S. Schreiber, Shail Aditya Gupta, Vinod K. Kathail, Santosh George Abraham, Bantwal Ramakrishna Rau
  • Patent number: 6651222
    Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: November 18, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shail Aditya Gupta, B. Ramakrishna Rau, Vinod K. Kathail, Michael S. Schlansker
  • Patent number: 6581187
    Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: June 17, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shail Aditya Gupta, B. Ramakrishna Rau, Vinod K. Kathail, Michael S. Schlansker
  • Patent number: 6507947
    Abstract: A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified design constraint. Another programmatic method synthesizes a processor array from the set of parallel processes and a specified design constraint.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: January 14, 2003
    Assignee: Hewlett-Packard Company
    Inventors: Robert S. Schreiber, B. Ramakrishna Rau, Shail Aditya Gupta, Vinod K. Kathail, Sadun Anik
  • Publication number: 20020133784
    Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.
    Type: Application
    Filed: February 6, 2002
    Publication date: September 19, 2002
    Inventors: Shail Aditya Gupta, B. Ramakrishna Rau, Vinod K. Kathail, Michael S. Schlansker