Patents by Inventor Vinod Kariat
Vinod Kariat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9129078Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.Type: GrantFiled: October 30, 2013Date of Patent: September 8, 2015Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, Vinod Kariat, King Ho Tam
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Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
Patent number: 8966421Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.Type: GrantFiled: September 10, 2013Date of Patent: February 24, 2015Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Igor Keller, Joel R. Phillips, King Ho Tam -
Patent number: 8694934Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: GrantFiled: May 21, 2012Date of Patent: April 8, 2014Assignee: Cadence Design Systems, Inc.Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Patent number: 8631369Abstract: In one embodiment of the invention, a method of statically analyzing an integrated circuit with process and environment variations is provided. The method includes characterizing each circuit cell of a cell library for a sensitivity to process parameter variations within a predetermined range; creating a timing graph corresponding to a netlist representing an integrated circuit design; along nodes of the timing graph, computing delay values including sensitivities to process variations; for each selected output node of the netlist, propagating a full timing value function with the sensitivities to the selected output nodes; and generating a parameterized timing report including the sensitivities to the process variations.Type: GrantFiled: December 30, 2010Date of Patent: January 14, 2014Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Joel R. Phillips, Igor Keller
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Patent number: 8595669Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.Type: GrantFiled: September 2, 2008Date of Patent: November 26, 2013Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, Vinod Kariat, King Ho Tam
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Patent number: 8566760Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: GrantFiled: May 21, 2012Date of Patent: October 22, 2013Assignee: Cadence Design Systems, Inc.Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Patent number: 8543954Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.Type: GrantFiled: September 2, 2008Date of Patent: September 24, 2013Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, Vinod Kariat, King Ho Tam
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Patent number: 8543952Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.Type: GrantFiled: November 4, 2011Date of Patent: September 24, 2013Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8533644Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.Type: GrantFiled: December 12, 2010Date of Patent: September 10, 2013Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Igor Keller, Joel R. Phillips, King Ho Tam
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Patent number: 8516420Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.Type: GrantFiled: August 31, 2007Date of Patent: August 20, 2013Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Igor Keller, Joel R. Phillips, King Ho Tam
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Patent number: 8504958Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.Type: GrantFiled: October 7, 2011Date of Patent: August 6, 2013Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Publication number: 20120304137Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: ApplicationFiled: May 21, 2012Publication date: November 29, 2012Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Publication number: 20120297357Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: ApplicationFiled: May 21, 2012Publication date: November 22, 2012Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Publication number: 20120210285Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.Type: ApplicationFiled: November 4, 2011Publication date: August 16, 2012Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8201113Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distribution show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.Type: GrantFiled: July 25, 2008Date of Patent: June 12, 2012Assignee: Cadence Design Systems, Inc.Inventors: Eddy Pramono, Yong Zhan, Vinod Kariat
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Publication number: 20120102449Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.Type: ApplicationFiled: October 7, 2011Publication date: April 26, 2012Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8103996Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.Type: GrantFiled: April 1, 2009Date of Patent: January 24, 2012Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8104007Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.Type: GrantFiled: June 24, 2008Date of Patent: January 24, 2012Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Eddy Pramono, Yong Zhan
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Patent number: 8104006Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.Type: GrantFiled: January 31, 2008Date of Patent: January 24, 2012Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Igor Keller, Eddy Pramono
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Patent number: 7900166Abstract: A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.Type: GrantFiled: June 27, 2007Date of Patent: March 1, 2011Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Xiaopeng Dong, David Noice