Patents by Inventor Vinod Kathail

Vinod Kathail has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11687327
    Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: June 27, 2023
    Assignee: XILINX, INC.
    Inventors: Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig, Vinod Kathail
  • Publication number: 20220206766
    Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).
    Type: Application
    Filed: March 16, 2022
    Publication date: June 30, 2022
    Inventors: Chia-Jui HSU, Shail Aditya GUPTA, Samuel R. BAYLISS, Philip B. JAMES-ROXBY, Ralph D. WITTIG, Vinod KATHAIL
  • Patent number: 11281440
    Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 22, 2022
    Assignee: XILINX, INC.
    Inventors: Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig, Vinod Kathail
  • Publication number: 20220058005
    Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.
    Type: Application
    Filed: November 2, 2021
    Publication date: February 24, 2022
    Applicant: XILINX, INC.
    Inventors: Shail Aditya GUPTA, Samuel R. BAYLISS, Vinod KATHAIL, Ralph D. WITTIG, Philip B. JAMES-ROXBY, Akella SASTRY
  • Patent number: 10802807
    Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 13, 2020
    Assignee: XILINX, INC.
    Inventors: Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig, Vinod Kathail
  • Patent number: 6023751
    Abstract: A computer system provides fast evaluation of predicates and Boolean expressions with a set of operations for determining a value in a specified register from a plurality of inputs. The execution of each operation is defined by two functions of the operation's inputs: a result function which yields a result value, and an enable function which determines whether the result value is written to the specified register. To evaluate a Boolean expression with the operations, the register is preset to a Boolean value, e.g. one for an AND reduction, zero for an OR reduction. The operations can then write a Boolean value, e.g. zero for an AND reduction, one for an OR reduction, to the register if each operation's enable function evaluates true. The register then stores the correct value of the expression. The expression's value can be used as predicates to conditionally execute operations in a program.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: February 8, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Michael Schlansker, B. Ramakrishna Rau, Vinod Kathail
  • Patent number: 5999738
    Abstract: A technique for flexible scheduling of a code sequence wherein a set of instructions for determining a a fully-resolved predicate for each of a set of non-speculative instructions contained in the code sequence is generated. An optimized code sequence is then generated that includes the instructions for determining the fully resolved predicates and that further includes the non-speculative instructions each guarded by one of the fully resolved predicates such that any one of the non-speculative instructions may be executed before any other of the non-speculative instructions.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: December 7, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Michael S. Schlansker, Vinod Kathail
  • Patent number: 5850553
    Abstract: A compiler technique for reducing the number of executed branches in a code sequence. Multiple condition branch instructions in a program sequence are replaced with a single combined conditional branch instruction thereby eliminating the time-consuming execution of multiple branch instructions by a target processor.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: December 15, 1998
    Assignee: Hewlett-Packard Company
    Inventors: Michael S. Schlansker, Vinod Kathail
  • Patent number: 5664135
    Abstract: An improved computer architecture and instruction set that reduces the delays produced by branch instructions. The invention utilizes a branch processor having a branch memory for storing information specifying a plurality of branch instructions that are contained in a code sequence. The branch memory stores information specifying the target address of each branch instruction and the location of the branch instruction with respect to the beginning of the code sequence. The branch processor receives the results of the various comparisons that determine if the conditions associated with the various branches stored in the branch memory are satisfied. The branch processor preferably stores the identity of the branch that is closed to the beginning of the code sequence for which the condition associated therewith has been satisfied. This branch will be referred to as the highest branch enabled.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: September 2, 1997
    Assignee: Hewlett-Packard Company
    Inventors: Michael S. Schlansker, Vinod Kathail