Abstract: A system comprises an image signal processor (ISP). The ISP is a discrete hardware unit and includes a line buffer, a memory controller, and one or more image processors. The memory controller is configured to allocate blocks within the line buffer to a plurality of contexts, and for each of the contexts: receive one or more lines of image data associated with a respective context and store the one or more lines of the image data associated with the context in a respective block allocated to the respective context. The one or more image processors of the ISP are configured to, for each respective context of the plurality of contexts, process the one or more lines of the image data associated with the respective context that are stored in the line buffer.

Abstract: Systems and techniques are described herein for processing image data. For instance, an apparatus for processing image data is provided. The apparatus may include an image-signal processor (ISP) configured to process first image data of a data stream and to process second image data of the data stream; and a reset controller configured to, in response to a detected error related to the first image data, reset the first image data in a memory of the ISP while maintaining the second image data in the memory of the ISP.

Abstract: Systems and techniques are described herein for processing image data. For instance, a method for processing image data is provided. The method may include receiving first image data related to a first image at an image-signal processor (ISP); receiving second image data related to a second image at the ISP; while receiving the first image data and the second image data, processing the first image data and the second image data at the ISP; and in response to receiving a last portion of the first image data, delaying flushing of the first image data from an internal buffer of the ISP while processing the second image data.

Abstract: Imaging systems and techniques are described. For example, an imaging system may receive raw image data captured using an image sensor. The imaging system may process the raw image data according to a first image signal processor (ISP) setting to generate a first image and process the raw image data according to a second ISP setting (that is distinct from the first ISP setting) to generate a second image. The imaging system may output the first image and the second image.

Abstract: A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.

Abstract: A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.