Abstract: A flash memory receives an internal data transfer command from a memory controller which causes the flash memory to copy data from one sector of the flash memory to another sector of the flash memory without presenting any data traffic to the bus. The internal data transfer command may optionally include a count field which causes the flash memory to transfer a plurality of adjacent sectors starting from a source address to a corresponding plurality of adjacent sectors starting at a destination address. The internal data transfer command is particularly useful for backing up the contents of a block prior to an erase operation. The internal data transfer command may also be used, if necessary, to restore the data subsequent to the erase operation.

Abstract: For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to cells in unselected erase sectors sharing the same bitlines.

Abstract: For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to cells in unselected erase sectors sharing the same bitlines.

Abstract: The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.

Abstract: A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.

Abstract: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Abstract: A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses.

Abstract: A method for programming multi-state floating gate transistor memory cells, also called multi-state flash cells, in a memory system is disclosed. The memory system includes control circuitry for controlling an array of multi-state flash cells which are arranged in blocks and connected together in rows and columns. The method is implemented as a series of programmable instructions stored and implemented in the memory system. According to the method groups of multi-state flash cells are incrementaly programmed. In each programming step the threshold voltage levels of the cells being programmed is raised only one state. Successive subgroups of cells are programmed to increase their threshold voltage levels in a step-by-step manner. The multi-state flash cells are programmed to store the desired data over several steps. Cells that are under-programmed in any step are reprogrammed before the method continues.

Abstract: A flash memory receives an internal data transfer command from a memory controller which causes the flash memory to copy data from one sector of the flash memory to another sector of the flash memory without presenting any data traffic to the bus. The internal data transfer command may optionally include a count field which causes the flash memory to transfer a plurality of adjacent sectors starting from a source address to a corresponding plurality of adjacent sectors starting at a destination address. The internal data transfer command is particularly useful for backing up the contents of a block prior to an erase operation. The internal data transfer command may also be used, if necessary, to restore the data subsequent to the erase operation.

Abstract: A method for programming multi-state floating gate transistor memory cells, also called multi-state flash cells, in a memory system is disclosed. The memory system includes control circuitry for controlling an array of multi-state flash cells which are arranged in blocks and connected together in rows and columns. The method is implemented as a series of programmable instructions stored and implemented in the memory system. According to the method groups of multi-state flash cells are incrementaly programmed. In each programming step the threshold voltage levels of the cells being programmed is raised only one state. Successive subgroups of cells are programmed to increase their threshold voltage levels in a step-by-step manner. The multi-state flash cells are programmed to store the desired data over several steps. Cells that are under-programmed in any step are reprogrammed before the method continues.

Abstract: A flash memory integrated circuit includes wordlines, bitlines, an array of floating gate transistor memory cells, and current limiters. Each floating transistor memory cell is coupled to one of the bitlines and one of the wordlines. The current limiters operate when the floating gate transistor memory cells are programmed to limit an amount of current that a defective transistor memory cell draws through the bitline coupled to the defective transistor memory cell.

Abstract: An apparatus and method for programming the memory cells of a multistate memory. The method involves the collapsing of data before transmitting to the memory cells. A controller generates optimized program pulses of high voltage to apply to the memory cells. The pulses vary in amplitude and time, depending on the state level being transitioned. Program verify is performed by reading the programmed data back into the controller where it is compared with the original value intended for programming. This compare operation modifies the data read and initial data to reflect which memory cells require further programming. The modified data is again collapsed and sent to the memory for further programming and verify cycles until a monitoring circuit within the controller detects that no further programming is required.

Abstract: Healing cells in a memory device. According to one embodiment of the present invention a heal operation is performed on a plurality of cells in the memory device, a number of subsets of the cells that are leaking is counted where a subset of cells that is leaking includes a cell that conducts more than a predetermined amount of current when not being activated, and another heal operation is performed on the cells based on the number of subsets of the cells that are leaking.

Abstract: A charge pump employs N pump stages to transform an input supply voltage to a pump output voltage, such as a programming voltage used in a non-volatile memory. Each pump stage receives a stage input voltage and provides a stage output voltage. A first pump stage receives the input supply voltage as its stage input voltage. An output transistor is configured as an output diode coupled between the Nth stage output voltage and the pump output voltage. The output transistor has a threshold voltage which produces a voltage drop across the output diode. An output threshold voltage canceler compensates for the threshold voltage of the output transistor.

Abstract: A voltage of a relatively large potential internal signal in an integrated circuit is tested by providing a comparison signal having a voltage that is lower than the voltage of the relatively large potential internal signal. The voltage of the relatively large potential internal signal is scaled so that the voltage of the scaled internal signal is lower than the voltage of the relatively large potential internal signal. The voltages of the scaled internal signal and the comparison signal are compared. In another form of the invention, a voltage of a negative potential internal signal in an integrated circuit is tested by providing a comparison signal having a voltage higher than the ground potential. The voltage of the negative potential internal signal is converted to a voltage higher than the ground potential. The voltages of the converted internal signal and the comparison signal are compared.

Abstract: A standard single well (e.g., n-well) complementary metal-oxide-semiconductor (CMOS) process compatible voltage pump switch routes -10 Volt for erasing a floating gate transistor when an IC substrate is grounded at 0 Volts. The voltage pump switch also routes extreme positive voltages for programming or reading the floating gate transistor. P-channel field-effect transistors (PFETs) multiplex both the read/write/programming and erasing voltages, such as in a block-erasable flash electrically erasable and programmable read only memory (EEPROM). The voltage pump switch includes a charge pump for providing to the PFET routing the erasing voltage a gate voltage that is more negative than the erasing voltage by the PFET turn-on threshold voltage (V.sub.T) magnitude.

Abstract: A flash memory integrated circuit includes wordlines, bitlines, an array of floating gate transistor memory cells, and current limiters. Each floating transistor memory cell is coupled to one of the bitlines and one of the wordlines. The current limiters operate when the floating gate transistor memory cells are programmed to limit an amount of current that a defective transistor memory cell draws through the bitline coupled to the defective transistor memory cell.

Abstract: A standard single well (e.g., n-well) complementary metal-oxide-semiconductor (CMOS) process compatible voltage pump switch routes -10 Volt for erasing a floating gate transistor when an IC substrate is grounded at 0 Volts. The voltage pump switch also routes extreme positive voltages for programming or reading the floating gate transistor. P-channel field-effect transistors (PFETs) multiplex both the read/write/programming and erasing voltages, such as in a block-erasable flash electrically erasable and programmable read only memory (EEPROM). The voltage pump switch includes a charge pump for providing to the PFET routing the erasing voltage a gate voltage that is more negative than the erasing voltage by the PFET turn-on threshold voltage (V.sub.T) magnitude.

Abstract: A memory is described which uses floating gate transistors as memory cells in a memory array. The memory array has blocks of memory cells coupled to a common bitline. A voltage control circuit is described which provides reference voltages for reducing voltage disturbances in non-selected memory cells while selected memory cells are being programmed.

Abstract: A voltage of a relatively large potential internal signal in an integrated circuit is tested by providing a comparison signal having a voltage that is lower than the voltage of the relatively large potential internal signal. The voltage of the relatively large potential internal signal is scaled so that the voltage of the scaled internal signal is lower than the voltage of the relatively large potential internal signal. The voltages of the scaled internal signal and the comparison signal are compared. In another form of the invention, a voltage of a negative potential internal signal in an integrated circuit is tested by providing a comparison signal having a voltage higher than the ground potential. The voltage of the negative potential internal signal is converted to a voltage higher than the ground potential. The voltages of the converted internal signal and the comparison signal are compared.