Patents by Inventor Vinod Narayanan

Vinod Narayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220378008
    Abstract: Systems and methods are provided for controlling heat stress and accumulations in livestock using the application of water sprays onto the animal in conjunction with fan induced airflow. The system has a controller with sensor inputs of the ambient environment including temperature, humidity, wind speed, and surrounding surface temperature sensors and fan and spray control outputs. To achieve savings in water and electricity, a transient, one-dimensional simultaneous heat and mass transfer model of evaporation within the wetted fur layer of a dairy cow is used to estimate drying time and heat rejection rate based on ambient conditions along with a control algorithm to predict the fan speed and sprinkler operation frequency needed to meet specified cooling load thresholds given the outdoor conditions. Estimated savings demonstrated that the model-based controller could reduce annual electricity and water consumption by 20% and 40%, respectively.
    Type: Application
    Filed: September 22, 2020
    Publication date: December 1, 2022
    Applicant: The Regents of the University of California
    Inventors: Theresa Pistochini, Elizabeth Chen, Vinod Narayanan
  • Publication number: 20220010981
    Abstract: The disclosed embodiments relate to a system that provides a polymer heat exchanger with internal microscale flow passages. The system includes a set of plates comprised of a polymer that includes internal microscale flow passages, which are configured to carry a liquid. The set of plates is organized into a stack, wherein consecutive plates in the stack are separated by fins to form intervening air passages. The system includes a liquid flow pathway, which flows from a liquid inlet, through the internal microscale flow passages in the stack of plates, to a liquid outlet. It also includes an airflow pathway, which flows from an airflow inlet, through the intervening air passages between the consecutive plates in the stack of plates, to an airflow outlet. The liquid flow pathway flows in a direction opposite to a direction of the airflow pathway to provide a counterflow design that optimizes heat transfer between the liquid flow pathway and the airflow pathway.
    Type: Application
    Filed: January 13, 2021
    Publication date: January 13, 2022
    Applicant: The Regents of the University of California
    Inventors: Vinod Narayanan, Erfan Rasouli
  • Publication number: 20210055063
    Abstract: An apparatus with a first pathway configured to circulate a first substance and a second pathway configured to circulate a second substance between a plurality of plates. The first pathway includes: a plurality of plates with a plurality of flow channels; a first inlet configured to receive the first substance and provide the first substance to the first plurality of flow channels; and a first outlet configured to receive the first substance from the first plurality of flow channels. The second pathway includes: a second inlet configured to receive the second substance; and a second outlet configured to output the second substance.
    Type: Application
    Filed: September 11, 2020
    Publication date: February 25, 2021
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, CARNEGIE MELLON UNIVERSITY
    Inventors: Vinod Narayanan, Erfan Rasouli, Anthony Rollett, Samikshya Subedi
  • Patent number: 10619890
    Abstract: A thermal receiver, such as a solar flux thermal receiver, is disclosed comprising a modular arrangement of arrayed microchannels or micropins to heat a working fluid by heat transfer. Disclosed solar receivers provide a much higher solar flux and consequently a significant reduction in thermal losses, size, and cost, relative to known receivers. Unit cell receivers can be numbered up and combined in parallel to form modules, and modules combined to form full scale receivers.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: April 14, 2020
    Assignees: Oregon State University, The Regents of the University of California
    Inventors: Monte Kevin Drost, Sourabh Apte, Thomas L'Estrange, Vinod Narayanan, Charles Rymal, Eric Truong, Erfan Rasouli, Kyle Ryan Zada, Brian M. Fronk
  • Publication number: 20180010824
    Abstract: A thermal receiver, such as a solar flux thermal receiver, is disclosed comprising a modular arrangement of arrayed microchannels or micropins to heat a working fluid by heat transfer. Disclosed solar receivers provide a much higher solar flux and consequently a significant reduction in thermal losses, size, and cost, relative to known receivers. Unit cell receivers can be numbered up and combined in parallel to form modules, and modules combined to form full scale receivers.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 11, 2018
    Applicants: Oregon State University, Regents of the University of California
    Inventors: Monte Kevin Drost, Sourabh Apte, Thomas L'Estrange, Vinod Narayanan, Charles Rymal, Eric Truong, Erfan Rasouli, Kyle Ryan Zada, Brian M. Fronk
  • Publication number: 20150010874
    Abstract: A miniaturized power generation device and method are provided. In one configuration a microscale combustor and heat exchanger may include several repeating unit cells each of which performs combustion, recuperation, and heat exchange. Catalytic combustion may occur inside at least one combustion and one recuperator channel. Specific features may be added to reduce heat loss and pressure drop.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Inventors: Mohammad Ghazvini, Vinod Narayanan, Monte Kevin Drost, Brian K. Paul
  • Patent number: 7434411
    Abstract: Microchannel or fractal plate desorption retains the advantage of high-flux, thin-film desorption without using membranes and allows for lightweight, compact desorbers for either LiBr and water or ammonia and water. Working embodiments of the process comprise providing a droplet desorber, feeding a multicomponent fluid mixture comprising at least a first fluid and a second fluid to the desorber, and performing a desorption process on the mixture using the desorber. The primary fluid mixtures used were ammonia and water, and aqueous lithium bromide. Various working embodiments of desorbers are disclosed, including several desorbers comprising plural, substantially straight, substantially parallel microchannels in an array, and a fractal plate desorber, such as a bifurcating fractal plate.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: October 14, 2008
    Inventors: Kevin M. Drost, Vinod Narayanan, Deborah V. Pence
  • Publication number: 20050126211
    Abstract: Microchannel or fractal plate desorption retains the advantage of high-flux, thin-film desorption without using membranes and allows for lightweight, compact desorbers for either LiBr and water or ammonia and water. Working embodiments of the process comprise providing a droplet desorber, feeding a multicomponent fluid mixture comprising at least a first fluid and a second fluid to the desorber, and performing a desorption process on the mixture using the desorber. The primary fluid mixtures used were ammonia and water, and aqueous lithium bromide. Various working embodiments of desorbers are disclosed, including several desorbers comprising plural, substantially straight, substantially parallel microchannels in an array, and a fractal plate desorber, such as a bifurcating fractal plate.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 16, 2005
    Inventors: Kevin Drost, Vinod Narayanan, Deborah Pence
  • Patent number: 6131182
    Abstract: A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs.
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: October 10, 2000
    Assignee: International Business Machines Corporation
    Inventors: Michael Patrick Beakes, Barbara Alana Chappell, Terry Ivan Chappell, Gary S. Ditlow, Barry Lee Dorfman, Bruce Martin Fleischer, Vinod Narayanan, Robert Alan Philhower, George Anthony Sai Halasz, Ghavam Ghavami Shahidi, David James Widiger
  • Patent number: 6005416
    Abstract: A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems.
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: December 21, 1999
    Assignee: International Business Machines Corporation
    Inventors: Michael Patrick Beakes, Barbara Alana Chappell, Terry Ivan Chappell, Gary S. Ditlow, Barry Lee Dorfman, Bruce Martin Fleischer, Vinod Narayanan, David James Widiger
  • Patent number: 5761664
    Abstract: A computer model for facilitating computer assisted design includes data structures which are flexibly organized by storing of information in accordance with entities or simulations thereof (including symbolic layer entities, area entities, area spec entities and area spec usage pattern entities), which are hierarchically associated both by relationships between them at a given level of abstraction of the physical entity they represent and by various attributes that correspond to different levels of abstraction in graphs. The graphs are freely mappable onto any desired fixed data structure such as a hierarchical area tree. Each hierarchical level and particularly the symbolic layer entity within the computer model provides data hiding at each lower level thereof and thus provides data hiding in the fixed data structure by virtue of the mapping function in order to reduce data processing overhead for manipulation of the fixed data structure.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: John Sayah, Vinod Narayanan, Philip Honsinger
  • Patent number: 5648912
    Abstract: A method for assigning interconnection resources to input/output connection points on differential current switch logic elements which need to use the resources, but which introduce an order dependency to the assignment problem, due to restrictions unique to differential current logic. The input/output connection points are paired first as are the interconnection resources. Pairing removes the order dependency. An assignment is then made through the use of an optimizing linear assignment algorithm suitable for single input/output connection point to single interconnection resource assignments. Preferably, a cost matrix is generated to determine the optimum assignment by minimizing the total assignment cost. The paired assignments are then broken apart to assign each individual member of the point pair to an individual member of the assigned resource pair.
    Type: Grant
    Filed: April 12, 1993
    Date of Patent: July 15, 1997
    Assignee: International Business Machines Corporation
    Inventors: Vinod Narayanan, Philip S. Honsinger, Lok Tin Liu
  • Patent number: 5500804
    Abstract: A wiring methodology for optimizing the wiring of multiple wiring media packages. Data models are created for the package and for the networks which embody the circuit design logic of the package. These data models represent the design data and the contrasting electrical and geometrical characteristics of the different media in a form suitable for the operation of wiring algorithms. In the preferred embodiment, one or more constraint models are associated with each wiring network. The electrical properties and availability limits of all wiring resources are included in the data model. The data model is then used in the selection of a rough path for each connection and the assignment of networks and portions of networks to particular media. The rough path serves as a basis for estimates of the characteristics of the wiring solution for each network.
    Type: Grant
    Filed: December 8, 1993
    Date of Patent: March 19, 1996
    Assignee: International Business Machines Corporation
    Inventors: Philip S. Honsinger, Lucy Lim, Vinod Narayanan
  • Patent number: 5360767
    Abstract: A method of assigning pins to corresponding connection points in the design of computer modules where connection points on one layer need to be electrically connected through the pins to a wiring layer so as to minimize the length of the wiring between the points. A best area for selecting a pin is identified for each point that needs to use a pin, and pins are preferentially assigned to the points from their respective best areas. The method introduces a consideration of the direction of the destination point into the assignment solution and allows previous assignment methods to be used which incorrectly assumed that the direction to the destination point could be ignored.
    Type: Grant
    Filed: April 12, 1993
    Date of Patent: November 1, 1994
    Assignee: International Business Machines Corporation
    Inventors: Vinod Narayanan, Philip Honsinger, Lok T. Lui, Shuhui Lin