Patents by Inventor Vinod Narippatta

Vinod Narippatta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230198622
    Abstract: A method includes receiving client data; extracting overhead data from the client data; mapping the client data into one or more frames, where each of the one or more frames has a frame payload section and a frame overhead section, where the client data is mapped into the one or more frames; inserting the overhead data into the frame overhead section of the one or more frames; transporting the one or more frames across a network by generating a plurality of optical subcarriers carrying the one or more frames; extracting the overhead data from the frame overhead section of the one or more frames; recovering the client data from the one or more frames; inserting the extracted overhead data into the recovered client data to create modified client data; and outputting the modified client data.
    Type: Application
    Filed: March 25, 2022
    Publication date: June 22, 2023
    Applicant: Infinera Corporation
    Inventors: Radhakrishna Valiveti, Rajan Rao, Vinod Narippatta, Sharfuddin Syed, Parthiban Kandappan
  • Patent number: 10331601
    Abstract: Methods and apparatuses for data transformation are disclosed. An exemplary apparatus includes a first memory, a second memory, a cross-bar switch communicatively coupled between the first memory and the second memory, and a lookup table that specifies one or more memory addresses of the first memory to read out to the cross-bar switch, one or more memory addresses of the second memory to which to write data from the cross-bar switch, and a configuration of the cross-bar switch. An exemplary method includes determining, based on a lookup table, one or more memory addresses of a first memory to read out to a cross-bar switch, determining, based on the lookup table, one or more memory addresses of a second memory to which to write data from the cross-bar switch, and determining, based on the lookup table, a configuration of the cross-bar switch.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: June 25, 2019
    Assignee: Infinera Corporation
    Inventors: Vinod Narippatta, Unnikrishnan C V, Sanjay Kamat, Ashok Jain, Ashok Tatineni, Vishwanathan Paramasivam
  • Patent number: 10103869
    Abstract: Systems, apparatus, and methods for packetized clocks may include a packet interface to carry the rate of a client to a sigma-delta modulator that generates a clock at the required rate inside the chip itself there by removing the need for off-chip analog PLLs. The packetized clock may include a packet interface that receives a flow credit packet that includes a plurality of flow credit counts, one flow credit count for each data flow, and forwards a flow credit count for each data flow to one of a plurality of clock generators to generate a new clock signal for each data flow.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 16, 2018
    Assignee: Infinera Corporation
    Inventors: Vinod Narippatta, Mohammed Asad Rizvi
  • Publication number: 20170300443
    Abstract: Methods and apparatuses for data transformation are disclosed. An exemplary apparatus includes a first memory, a second memory, a cross-bar switch communicatively coupled between the first memory and the second memory, and a lookup table that specifies one or more memory addresses of the first memory to read out to the cross-bar switch, one or more memory addresses of the second memory to which to write data from the cross-bar switch, and a configuration of the cross-bar switch. An exemplary method includes determining, based on a lookup table, one or more memory addresses of a first memory to read out to a cross-bar switch, determining, based on the lookup table, one or more memory addresses of a second memory to which to write data from the cross-bar switch, and determining, based on the lookup table, a configuration of the cross-bar switch.
    Type: Application
    Filed: August 26, 2016
    Publication date: October 19, 2017
    Inventors: Vinod NARIPPATTA, Unnikrishnan C. V, Sanjay KAMAT, Ashok JAIN, Ashok TATINENI, Vishwanathan PARAMASIVAM
  • Publication number: 20170302434
    Abstract: Systems, apparatus, and methods for packetized clocks may include a packet interface to carry the rate of a client to a sigma-delta modulator that generates a clock at the required rate inside the chip itself there by removing the need for off-chip analog PLLs. The packetized clock may include a packet interface that receives a flow credit packet that includes a plurality of flow credit counts, one flow credit count for each data flow, and forwards a flow credit count for each data flow to one of a plurality of clock generators to generate a new clock signal for each data flow.
    Type: Application
    Filed: August 26, 2016
    Publication date: October 19, 2017
    Inventors: Vinod Narippatta, Mohammed Asad Rizvi
  • Patent number: 9756406
    Abstract: Systems, apparatus, and methods for a configurable gearbox with a variable number of input lanes and output lanes and a multiplexer for each output lane that can be configured to dynamically select any of the input lanes during each clock cycle.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: September 5, 2017
    Assignee: Infinera Corporation
    Inventor: Vinod Narippatta
  • Patent number: 8848720
    Abstract: A propagation delay in the transmission of a frame from an initiator node to a peer node is determined by initially identifying a frame number and byte offset of a first incoming frame from the peer node at a time when the initiator node outputs a portion of a transmitted frame. The portion of the transmitted frame may be the first byte of a sub-frame within the transmitted frame. At the peer node, the frame number and byte offset of a second frame to be supplied to the initiator node is identified at a later time when the frame portion transmitted by the initiator node is received by the peer node, and such information is transmitted to the initiator node. Thus, since the frames output and received by the initiator node are typically of fixed duration, the frame number and byte offset of the incoming frame represent the time when the initiator node outputs the frame portion (a transmit time).
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: September 30, 2014
    Assignee: Infinera Corporation
    Inventors: Vinod Narippatta, Edward E. Sprague, Ting-Kuang Chiang, Chung Kuang Chin
  • Publication number: 20110235646
    Abstract: A propagation delay in the transmission of a frame from an initiator node to a peer node is determined by initially identifying a frame number and byte offset of a first incoming frame from the peer node at a time when the initiator node outputs a portion of a transmitted frame. The portion of the transmitted frame may be the first byte of a sub-frame within the transmitted frame. At the peer node, the frame number and byte offset of a second frame to be supplied to the initiator node is identified at a later time when the frame portion transmitted by the initiator node is received by the peer node, and such information is transmitted to the initiator node. Thus, since the frames output and received by the initiator node are typically of fixed duration, the frame number and byte offset of the incoming frame represent the time when the initiator node outputs the frame portion (a transmit time).
    Type: Application
    Filed: March 25, 2010
    Publication date: September 29, 2011
    Inventors: Vinod Narippatta, Edward E. Sprague, Ting-Kuang Chiang, Chung Kuang Chin