Patents by Inventor Vinod Pisharath Hari PAI

Vinod Pisharath Hari PAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processing apparatus, controller, cache and method
    Patent number: 10250709
    Abstract: A data processing apparatus has multiple caches and a controller for controlling the caches. The controller and caches communicate over a first network and a second network. The first network is used for unicast communication from the controller to a specific one of the caches. The second network is used for communication of a multicast communication from the controller to two or more of the caches.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: April 2, 2019
    Assignee: Arm Limited
    Inventors: Jesus Javier de los Reyes Darias, Hakan Persson, Roko Grubisic, Vinod Pisharath Hari Pai
  • Multiple stage memory management
    Patent number: 9996474
    Abstract: A multiple stage memory management unit (MMU) comprises a first MMU stage configured to translate an input virtual memory address to a corresponding intermediate memory address, the first MMU stage generating a set of two or more intermediate memory addresses including the corresponding intermediate memory address; and a second MMU stage configured to translate an intermediate memory address provided by the first MMU stage to a physical memory address, the second MMU stage providing, in response to an intermediate memory address received from the first MMU stage, a set of two or more physical memory addresses including the physical memory address corresponding to the intermediate memory address received from the first MMU stage; the first MMU stage being configured to provide to the second MMU stage for translation, intermediate memory addresses in the set other than any intermediate memory addresses in the set for which the second MMU stage will provide a physical memory address as a response to translation
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 12, 2018
    Assignee: Arm Limited
    Inventors: Vahan Ter-Grigoryan, Hakan Lars-Goran Persson, Jesus Javier de los Reyes Darias, Vinod Pisharath Hari Pai
  • DATA PROCESSING APPARATUS, CONTROLLER, CACHE AND METHOD
    Publication number: 20160323407
    Abstract: A data processing apparatus has multiple caches and a controller for controlling the caches. The controller and caches communicate over a first network and a second network. The first network is used for unicast communication from the controller to a specific one of the caches. The second network is used for communication of a multicast communication from the controller to two or more of the caches.
    Type: Application
    Filed: April 14, 2016
    Publication date: November 3, 2016
    Applicant: ARM Limited
    Inventors: Jesus Javier de los REYES DARIAS, Hakan PERSSON, Roko GRUBISIC, Vinod Pisharath Hari PAI
  • MEMORY MANAGEMENT
    Publication number: 20160283396
    Abstract: A multiple stage memory management unit (MMU) comprises a first MMU stage configured to translate an input virtual memory address to a corresponding intermediate memory address, the first MMU stage generating a set of two or more intermediate memory addresses including the corresponding intermediate memory address; and a second MMU stage configured to translate an intermediate memory address provided by the first MMU stage to a physical memory address, the second MMU stage providing, in response to an intermediate memory address received from the first MMU stage, a set of two or more physical memory addresses including the physical memory address corresponding to the intermediate memory address received from the first MMU stage; the first MMU stage being configured to provide to the second MMU stage for translation, intermediate memory addresses in the set other than any intermediate memory addresses in the set for which the second MMU stage will provide a physical memory address as a response to translation
    Type: Application
    Filed: March 22, 2016
    Publication date: September 29, 2016
    Applicant: ARM Limited
    Inventors: Vahan TER-GRIGORYAN, Hakan Lars-Goran PERSSON, Jesus Javier de los REYES DARIAS, Vinod Pisharath Hari PAI