Patents by Inventor Vinod Robert Purayath
Vinod Robert Purayath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10790298Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. The method includes depositing in a stack of alternating insulator layers and memory cell layers a layer of silicon oxide, a layer of silicon nitride, and a layer of amorphous silicon; removing the layer of amorphous silicon while maintaining the layer of amorphous silicon in a recess of the memory cells; selectively oxidizing the layer of amorphous silicon and the layer of silicon nitride to remove the layer of amorphous silicon from the recess and the layer of silicon nitride from the insulator layers; and removing oxidizing material from the recess and the insulator layers such that the layer of silicon nitride remains only in the recess of each memory cell of the memory cell layers and the layer of silicon oxide remains on both the insulator layers and the memory cell layers.Type: GrantFiled: February 6, 2019Date of Patent: September 29, 2020Assignee: APPLIED MATERIALS, INC.Inventor: Vinod Robert Purayath
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Publication number: 20200227433Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. The method includes depositing in a stack of alternating insulator layers and memory cell layers a layer of silicon oxide, a layer of silicon nitride, and a layer of amorphous silicon; removing the layer of amorphous silicon while maintaining the layer of amorphous silicon in a recess of the memory cells; selectively oxidizing the layer of amorphous silicon and the layer of silicon nitride to remove the layer of amorphous silicon from the recess and the layer of silicon nitride from the insulator layers; and removing oxidizing material from the recess and the insulator layers such that the layer of silicon nitride remains only in the recess of each memory cell of the memory cell layers and the layer of silicon oxide remains on both the insulator layers and the memory cell layers.Type: ApplicationFiled: February 6, 2019Publication date: July 16, 2020Inventor: VINOD ROBERT PURAYATH
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Publication number: 20200051994Abstract: A method of forming a memory device including a plurality of nonvolatile memory cells is provided. The method includes forming a hole in a stack of alternating insulator layers and memory cell layers. The stack extends from a bottom to a top, and the stack includes a plurality of insulator layers and plurality of memory cell layers. The method further includes depositing a first portion of a silicon channel layer. The first portion of the silicon channel layer extends from the bottom of the stack to the top of the stack. The method further includes adding a dopant layer over the first portion of the silicon channel layer. The dopant layer includes a first dopant. The method further includes depositing a second portion of the silicon channel layer. The second portion of the silicon channel layer extends from the bottom of the stack to the top of the stack.Type: ApplicationFiled: October 3, 2018Publication date: February 13, 2020Inventors: Vinod Robert PURAYATH, Priyadarshi PANDA, Abhijit MALLICK, Srinivas GANDIKOTA
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Patent number: 10468259Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.Type: GrantFiled: April 30, 2018Date of Patent: November 5, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Vinod Robert Purayath, Nitin K. Ingle
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Publication number: 20180254187Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.Type: ApplicationFiled: April 30, 2018Publication date: September 6, 2018Inventors: Vinod Robert PURAYATH, Nitin K. INGLE
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Patent number: 9960045Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.Type: GrantFiled: February 2, 2017Date of Patent: May 1, 2018Assignee: Applied Materials, Inc.Inventors: Vinod Robert Purayath, Nitin K. Ingle
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Patent number: 9698149Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.Type: GrantFiled: January 13, 2015Date of Patent: July 4, 2017Assignee: SanDisk Technologies LLCInventors: Vinod Robert Purayath, George Matamis, Henry Chien, James Kai, Yuan Zhang
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Patent number: 9379120Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.Type: GrantFiled: July 22, 2013Date of Patent: June 28, 2016Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, Tuan Pham, Hiroyuki Kinoshita, Yuan Zhang, Henry Chin, James K Kai, Takashi W Orimoto, George Matamis, Henry Chien
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Publication number: 20150123191Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.Type: ApplicationFiled: January 13, 2015Publication date: May 7, 2015Applicant: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, George Matamis, Henry Chien, James Kai, Yuan Zhang
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Patent number: 8946048Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.Type: GrantFiled: June 16, 2011Date of Patent: February 3, 2015Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, George Matamis, Henry Chien, James Kai, Yuan Zhang
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Patent number: 8946803Abstract: Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.Type: GrantFiled: December 6, 2007Date of Patent: February 3, 2015Assignee: SanDisk Technologies Inc.Inventors: George Matamis, Henry Chien, Vinod Robert Purayath, Takashi Whitney Orimoto, James Kai
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Patent number: 8946022Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.Type: GrantFiled: February 22, 2013Date of Patent: February 3, 2015Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, James K Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
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Patent number: 8803220Abstract: Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.Type: GrantFiled: August 23, 2013Date of Patent: August 12, 2014Assignee: SanDisk Technologies Inc.Inventors: Takashi Whitney Orimoto, Atsushi Suyama, Ming Tian, Henry Chin, Henry Chien, Vinod Robert Purayath, Dana Lee
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Publication number: 20130341700Abstract: Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.Type: ApplicationFiled: August 23, 2013Publication date: December 26, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: Takashi Whitney Orimoto, Atsushi Suyama, Ming Tian, Henry Chin, Henry Chien, Vinod Robert Purayath, Dana Lee
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Publication number: 20130334587Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.Type: ApplicationFiled: July 22, 2013Publication date: December 19, 2013Applicant: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, Tuan Pham, Hiroyuki Kinoshita, Yuan Zhang, Henry Chin, James K. Kai, Takashi W. Orimoto, George Matamis, Henry Chien
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Patent number: 8603890Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.Type: GrantFiled: June 16, 2011Date of Patent: December 10, 2013Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, George Matamis, Eli Harari, Hiroyuki Kinoshita, Tuan Pham
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Patent number: 8546152Abstract: A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.Type: GrantFiled: December 19, 2007Date of Patent: October 1, 2013Assignee: SanDisk Technologies Inc.Inventors: Takashi Orimoto, George Matamis, James Kai, Vinod Robert Purayath
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Patent number: 8546214Abstract: Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.Type: GrantFiled: September 21, 2010Date of Patent: October 1, 2013Assignee: SanDisk Technologies Inc.Inventors: Takashi Whitney Orimoto, Atsushi Suyama, Ming Tian, Henry Chin, Henry Chien, Vinod Robert Purayath, Dana Lee
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Patent number: 8546239Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements.Type: GrantFiled: June 9, 2011Date of Patent: October 1, 2013Assignee: SanDisk Technologies Inc.Inventors: Eli Harari, Tuan Pham, Yupin Fong, Vinod Robert Purayath
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Patent number: 8492224Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.Type: GrantFiled: June 17, 2011Date of Patent: July 23, 2013Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, Tuan Pham, Hiroyuki Kinoshita, Yuan Zhang, Henry Chin, James K. Kai, Takashi W. Orimoto, George Matamis, Henry Chien