Abstract: Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL).

Abstract: Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL).

Abstract: Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a write operation to a subset of the memory cells, while preserving state-retention abilities of remaining ones of the plurality of memory cells. Weakening may include adjusting one or more resistances between one or more power supplies and the plurality of memory cells. Dynamic control may be selectively performed on portions of each of the memory cells in response to an input data logic state. Dynamic control may reduce a write contention within the subset of memory cells without disabling state-retention abilities of remaining ones of the plurality of memory cells, and may improve write response times of the memory cells.

Abstract: Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a write operation to a subset of the memory cells, while preserving state-retention abilities of remaining ones of the plurality of memory cells. Weakening may include adjusting one or more resistances between one or more power supplies and the plurality of memory cells. Dynamic control may be selectively performed on portions of each of the memory cells in response to an input data logic state. Dynamic control may reduce a write contention within the subset of memory cells without disabling state-retention abilities of remaining ones of the plurality of memory cells, and may improve write response times of the memory cells.