Patents by Inventor Vinod Sasidharan

Vinod Sasidharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10963592
    Abstract: A memory device operable in either of a Secure Digital operational mode and an NVMe operational mode includes password conversion logic to enable the memory device user-mode memory blocks to be accessed in the NVMe operational mode after the memory device was locked in the Secure Digital operational mode.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vinod Sasidharan, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Publication number: 20200250346
    Abstract: A memory device operable in either of a Secure Digital operational mode and an NVMe operational mode includes password conversion logic to enable the memory device user-mode memory blocks to be accessed in the NVMe operational mode after the memory device was locked in the Secure Digital operational mode.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Inventors: Vinod Sasidharan, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 10705902
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to store crash-dump information in a boot partition following a system crash within the data storage controller. Within illustrative examples described herein, the boot partition may be read by a host device without the host first re-installing valid firmware into the data storage controller following the system crash. In the illustrative examples, the data storage controller is configured for use with versions of Peripheral Component Interconnect (PCI) Express—Non-Volatile Memory express (NVMe) that provide support for boot partitions in the NVM. The illustrative examples additionally describe virtual boot partitions in random access memory (RAM) for storing crash-dump information if the NAND has been corrupted, where the crash-dump information is retrieved from the RAM without power-cycling the RAM.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: July 7, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vinod Sasidharan, Rishabh Mahajan, Abhishek Mourya
  • Patent number: 10649674
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND device or other non-volatile memory (NVM)—to retrieve configuration information from a NAND boot partition during an initialization procedure initiated by a host. Within illustrative examples described herein, the configuration information stored in the NAND boot partition is provided in addition to configuration information stored within physical layer register sets of the data storage controller. In the examples, the data storage controller is configured for use with versions of Peripheral Component Interconnect (PCI) Express—Non-Volatile Memory express (NVMe) that provide support for NAND boot partitions. In these examples, the use of the NAND boot partition allows an NVM device manufacturer to implement at least some new features in firmware or software within an existing NVM card, without modifying the physical layer registers.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 12, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vinod Sasidharan, Rishabh Mahajan, Abhishek Mourya
  • Patent number: 10564898
    Abstract: A method and apparatus for managing storage devices includes a host interface, a plurality of storage device interfaces, and a processor. The host interface is configured to communicatively couple with a host device and the plurality of storage interfaces configured to communicatively couple with storage devices. The processor is communicatively coupled to the host interface and the plurality of storage device interfaces. Further, the processor is configured to receive requests from the host device via the host interface and communicate the requests to the storage devices via the plurality of storage device interfaces. The processor is additionally configured to receive responses from the storage devices via the plurality of storage interfaces and communicate the responses to the host device via the host interface, manage a global submission queue and a global completion queue, and manage a submission queue and a completion queue for each of the storage devices.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Abhijit Rao, Vinod Sasidharan
  • Publication number: 20190377516
    Abstract: A method and apparatus for managing storage devices includes a host interface, a plurality of storage device interfaces, and a processor. The host interface is configured to communicatively couple with a host device and the plurality of storage interfaces configured to communicatively couple with storage devices. The processor is communicatively coupled to the host interface and the plurality of storage device interfaces. Further, the processor is configured to receive requests from the host device via the host interface and communicate the requests to the storage devices via the plurality of storage device interfaces. The processor is additionally configured to receive responses from the storage devices via the plurality of storage interfaces and communicate the responses to the host device via the host interface, manage a global submission queue and a global completion queue, and manage a submission queue and a completion queue for each of the storage devices.
    Type: Application
    Filed: August 10, 2018
    Publication date: December 12, 2019
    Inventors: Abhijit RAO, Vinod SASIDHARAN
  • Publication number: 20190339888
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND device or other non-volatile memory (NVM)—to retrieve configuration information from a NAND boot partition during an initialization procedure initiated by a host. Within illustrative examples described herein, the configuration information stored in the NAND boot partition is provided in addition to configuration information stored within physical layer register sets of the data storage controller. In the examples, the data storage controller is configured for use with versions of Peripheral Component Interconnect (PCI) Express—Non-Volatile Memory express (NVMe) that provide support for NAND boot partitions. In these examples, the use of the NAND boot partition allows an NVM device manufacturer to implement at least some new features in firmware or software within an existing NVM card, without modifying the physical layer registers.
    Type: Application
    Filed: May 3, 2018
    Publication date: November 7, 2019
    Inventors: Vinod Sasidharan, Rishabh Mahajan, Abhishek Mourya
  • Publication number: 20190340058
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to store crash-dump information in a boot partition following a system crash within the data storage controller. Within illustrative examples described herein, the boot partition may be read by a host device without the host first re-installing valid firmware into the data storage controller following the system crash. In the illustrative examples, the data storage controller is configured for use with versions of Peripheral Component Interconnect (PCI) Express—Non-Volatile Memory express (NVMe) that provide support for boot partitions in the NVM. The illustrative examples additionally describe virtual boot partitions in random access memory (RAM) for storing crash-dump information if the NAND has been corrupted, where the crash-dump information is retrieved from the RAM without power-cycling the RAM.
    Type: Application
    Filed: May 3, 2018
    Publication date: November 7, 2019
    Inventors: Vinod Sasidharan, Rishabh Mahajan, Abhishek Mourya