Patents by Inventor Vinodh Chandrasekaran
Vinodh Chandrasekaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200211729Abstract: A conductive paste for use in a laser-induced pattern transfer printing process includes a conductive component; a glass component; and an inorganic vehicle, wherein the conductive paste exhibits a light reflectance of no more than 50% across a light wavelength range of about 800 to about 1300 nm and improving the transfer of the paste to the substrate. A process for laser-induced pattern transfer printing includes providing a first substrate comprising a recessed surface and a conductive paste disposed in the recessed surface; orienting the recessed surface of the first substrate toward a second substrate; irradiating the conductive paste with a laser, the laser configured to emit light having a wavelength between about 800 and about 1300 nm; and transferring the irradiate conductive paste from the first substrate to a surface of the second substrate.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Vinodh Chandrasekaran, Matthias Hoerteis
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Publication number: 20190280134Abstract: The invention provides a method of preparing a metallization structure on a solar cell. The method includes patterning a first composition on a surface of a semiconductor substrate; and applying a second composition over the first composition. An area covered by the first composition is 5-95% of an area covered by the second composition. The semiconductor substrate is then subjected to firing conditions. The invention also provides a metallization structure formed using the method described herein.Type: ApplicationFiled: March 22, 2018Publication date: September 12, 2019Inventors: Li Yan, Vinodh Chandrasekaran, Lei Wang, Chi Long Chen, Lin Jiang, Cuiwen Guo, Weiming Zhang, Jing (Crystal) Han
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Publication number: 20190280133Abstract: The invention provides a seed layer paste for contacting a solar cell electrode with a low silver laydown and yet provides a higher voltage and a comparable solar efficiency. The seed layer paste includes: 1) a silver particle at 0.1-50 wt %; 2) at least one glass frit at 5-70 wt %; and 3) an organic vehicle at 20-95 wt %. The invention also provides a method of forming a solar cell by applying the seed layer paste of the invention to a surface of a silicon wafer to form a seed layer; applying on top of the seed layer a second composition containing a silver particle, at least one glass frit, and an organic vehicle; and firing the silicon wafer with the seed layer paste and the second composition.Type: ApplicationFiled: March 9, 2018Publication date: September 12, 2019Inventor: Vinodh Chandrasekaran
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Patent number: 9153728Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.Type: GrantFiled: January 9, 2012Date of Patent: October 6, 2015Assignee: Suniva, Inc.Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
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Patent number: 8921968Abstract: Solar cells and methods for their manufacture are disclosed. An example solar cell may comprise a substrate comprising a p-type base layer and an n-type selective emitter layer formed over the p-type base layer. The n-type selective emitter layer may comprise one or more first doped regions comprising implanted dopant and one or more second doped regions comprising diffused dopant. The one or more first doped regions may be more heavily doped than the one or more second doped regions. A p-n junction may be formed at the interface of the base layer and the selective emitter layer, such that the p-n junction and the selective emitter layer are both formed during a single anneal cycle.Type: GrantFiled: November 21, 2011Date of Patent: December 30, 2014Assignee: Suniva, Inc.Inventors: Ajeet Rohatgi, Vijay Yelundur, Preston Davis, Vinodh Chandrasekaran, Ben Damiani
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Publication number: 20140090702Abstract: Various embodiments of the present invention are directed to a reduced-area bus bar for collecting current from contacts on the surface of a solar cell. According to various embodiments described herein, a reduced-area bus bar is provided having a width that varies at various points along its longitudinal axis. In particular, the larger width portions of the reduced-area bus bar are configured to provide sufficient pull strength when an interconnecting ribbon is soldered along the bus bar, while the smaller width portions of the reduced-area bus bar enable a reduction in the material required to form the bus bar. Additionally, various embodiments are contemplated in which the reduced-area bus bar comprises a series of segments disposed in a spaced-apart relationship along the bus bar's longitudinal axis.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: Suniva, Inc.Inventors: Atul Gupta, Vinodh Chandrasekaran, John Roberts
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Publication number: 20120279563Abstract: Interconnect apparatus and methods for their manufacture are disclosed. An example method for forming a solderable connection to a conductive surface may include forming one or more solderable metal regions on the conductive surface, for example an aluminum surface. The method may comprise applying a solder layer to the one or more solderable metal regions to form one or more soldered metal regions. The method may further comprise depositing one or more solderable metal regions on the conductive surface by plasma deposition. In other examples, the one or more solderable metal regions may be sputtered. Additionally, the method may comprise applying a flux to the one or more solderable metal regions prior to applying the solder layer to the one or more solderable metal regions. An interconnect ribbon may be soldered to at least one of the solder layer or the solderable metal regions. Associated interconnect apparatus are also provided.Type: ApplicationFiled: May 2, 2011Publication date: November 8, 2012Inventors: Daniel Meier, Vijay Yelundur, Vinodh Chandrasekaran, Adam M. Payne, Sheri X. Wang
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Patent number: 8241945Abstract: Solar cells and methods for fabrication thereof are provided. A method may include forming a via through at least one dielectric layer formed on a semiconductor wafer by using a laser to ablate a region of the at least one dielectric layer such that at least a portion of the surface of the semiconductor wafer is exposed by the via. The method may further include applying a self-doping metal paste to the via. The method may additionally include heating the semiconductor wafer and self-doping metal paste to a temperature sufficient to drive at least some dopant from the self-doping metal paste into the portion of the surface of the semiconductor wafer exposed by the via to form a selective emitter region and a contact overlying and self-aligned to the selective emitter region.Type: GrantFiled: February 8, 2010Date of Patent: August 14, 2012Assignee: Suniva, Inc.Inventors: Adam M. Payne, Daniel L. Meier, Vinodh Chandrasekaran
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Publication number: 20120125416Abstract: Solar cells and methods for their manufacture are disclosed. An example solar cell may comprise a substrate comprising a p-type base layer and an n-type selective emitter layer formed over the p-type base layer. The n-type selective emitter layer may comprise one or more first doped regions comprising implanted dopant and one or more second doped regions comprising diffused dopant. The one or more first doped regions may be more heavily doped than the one or more second doped regions. A p-n junction may be formed at the interface of the base layer and the selective emitter layer, such that the p-n junction and the selective emitter layer are both formed during a single anneal cycle.Type: ApplicationFiled: November 21, 2011Publication date: May 24, 2012Applicant: SUNIVA, INC.Inventors: AJEET ROHATGI, VIJAY YELUNDUR, PRESTON DAVIS, VINODH CHANDRASEKARAN, BEN DAMIANI
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Publication number: 20120107998Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Applicant: SUNIVA, INC.Inventors: AJEET ROHATGI, VIJAY YELUNDUR, VINODH CHANDRASEKARAN, PRESTON DAVIS, BEN DAMIANI
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Patent number: 8110431Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a p-type doped silicon substrate and introducing n-type dopant to a first and second region of the front surface of the substrate by ion implantation so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to activate the dopant, drive the dopant into the substrate, produce a p-n junction, and form a selective emitter. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.Type: GrantFiled: June 3, 2010Date of Patent: February 7, 2012Assignee: Suniva, Inc.Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
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Patent number: 8071418Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a silicon substrate and introducing dopant to one or more selective regions of the front surface of the substrate by ion implantation. The substrate may be subjected to a single high-temperature anneal cycle. Additional dopant atoms may be introduced for diffusion into the front surface of the substrate during the single anneal cycle. A selective emitter may be formed on the front surface of the substrate such that the one or more selective regions of the selective emitter layer are more heavily doped than the remainder of the selective emitter layer. Associated solar cells are also provided.Type: GrantFiled: June 3, 2010Date of Patent: December 6, 2011Assignee: Suniva, Inc.Inventors: Ajeet Rohatgi, Vijay Yelundur, Preston Davis, Vinodh Chandrasekaran, Ben Damiani
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Publication number: 20110139231Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include fabricating an n-type silicon substrate and introducing n-type dopant to one or more first and second regions of the substrate so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to form a selective front surface field layer. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. The firing of the back contact may form a p+ emitter layer at the interface of the substrate and back contacts, thus forming a p-n junction at the interface of the emitter layer and the substrate. Associated solar cells are also provided.Type: ApplicationFiled: August 25, 2010Publication date: June 16, 2011Inventors: Daniel Meier, Ajeet Rohatgi, Vinodh Chandrasekaran, Vijay Yelundur, Preston Davis, Ben Damiani
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Publication number: 20110139230Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a p-type doped silicon substrate and introducing n-type dopant to a first and second region of the front surface of the substrate by ion implantation so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to activate the dopant, drive the dopant into the substrate, produce a p-n junction, and form a selective emitter. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.Type: ApplicationFiled: June 3, 2010Publication date: June 16, 2011Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
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Publication number: 20110139229Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a silicon substrate and introducing dopant to one or more selective regions of the front surface of the substrate by ion implantation. The substrate may be subjected to a single high-temperature anneal cycle. Additional dopant atoms may be introduced for diffusion into the front surface of the substrate during the single anneal cycle. A selective emitter may be formed on the front surface of the substrate such that the one or more selective regions of the selective emitter layer are more heavily doped than the remainder of the selective emitter layer. Associated solar cells are also provided.Type: ApplicationFiled: June 3, 2010Publication date: June 16, 2011Inventors: Ajeet Rohatgi, Vijay Yelundur, Preston Davis, Vinodh Chandrasekaran, Ben Damiani
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Publication number: 20110132448Abstract: Solar cells and methods for fabrication thereof are provided. A method may include forming a via through at least one dielectric layer formed on a semiconductor wafer by using a laser to ablate a region of the at least one dielectric layer such that at least a portion of the surface of the semiconductor wafer is exposed by the via. The method may further include applying a self-doping metal paste to the via. The method may additionally include heating the semiconductor wafer and self-doping metal paste to a temperature sufficient to drive at least some dopant from the self-doping metal paste into the portion of the surface of the semiconductor wafer exposed by the via to form a selective emitter region and a contact overlying and self-aligned to the selective emitter region.Type: ApplicationFiled: February 8, 2010Publication date: June 9, 2011Inventors: Adam M. Payne, Daniel L. Meier, Vinodh Chandrasekaran
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Publication number: 20110132444Abstract: Solar cells and methods for their manufacture are disclosed. An exemplary method may include providing a semiconductor substrate and introducing dopant atoms to a front surface of the substrate. The substrate may be annealed to drive the dopant atoms deeper in the substrate to produce a p-n junction while also forming front and back passivation layers. A reflective surface is sputtered on the back surface of the solar cell. It protects and generates hydrogen to passivate one or more substrate-passivation layer interfaces at the same time as forming an anti-reflective layer on the front surface of the substrate. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.Type: ApplicationFiled: January 8, 2010Publication date: June 9, 2011Inventors: Daniel L. Meier, Vinodh Chandrasekaran, Bruce McPherson
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Publication number: 20110114171Abstract: Solar cells and methods for their manufacture are disclosed. An exemplary method may include providing a semiconductor substrate and introducing dopant atoms to a front surface of the substrate. The substrate may be annealed to drive the dopant atoms deeper in the substrate to produce a p-n junction while also forming front and back passivation layers. A reflective surface is sputtered on the back surface of the solar cell. It protects and generates hydrogen to passivate one or more substrate-passivation layer interfaces at the same time as forming an anti-reflective layer on the front surface of the substrate. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.Type: ApplicationFiled: January 26, 2011Publication date: May 19, 2011Inventors: Daniel L. Meier, Vinodh Chandrasekaran, Bruce McPherson