Patents by Inventor Vinoo N. Srinivasan

Vinoo N. Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for layout synthesis of regular structures using relative placement
    Patent number: 7350174
    Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Vinoo N. Srinivasan, Veerapaneni Nagbhushan, Kumar Lalgudi
  • Method and apparatus for layout synthesis of regular structures using relative placement
    Publication number: 20040243963
    Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 2, 2004
    Inventors: Vinoo N. Srinivasan, Veerapaneni Nagbhushan, Kumar Lalgudi
  • Method and apparatus for layout synthesis of regular structures using relative placement
    Patent number: 6757878
    Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: June 29, 2004
    Assignee: Intel Corporation
    Inventors: Vinoo N. Srinivasan, Veerapaneni Nagbhushan, Kumar Lalgudi
  • Method and apparatus for layout synthesis of regular structures using relative placement
    Publication number: 20030126571
    Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventors: Vinoo N. Srinivasan, Veerapaneni Nagbhushan, Kumar Lalgudi