Patents by Inventor Vinoth Deivasigamani

Vinoth Deivasigamani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronous clock generator including duty cycle correction
    Publication number: 20060209620
    Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.
    Type: Application
    Filed: May 19, 2006
    Publication date: September 21, 2006
    Inventors: Vinoth Deivasigamani, Tyler Gomm
  • Synchronous clock generator including duty cycle correction
    Publication number: 20060202732
    Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.
    Type: Application
    Filed: May 3, 2006
    Publication date: September 14, 2006
    Inventors: Vinoth Deivasigamani, Tyler Gomm
  • Synchronous clock generator including duty cycle correction
    Publication number: 20060145745
    Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Vinoth Deivasigamani, Tyler Gomm