Abstract: A method includes executing, on a processor of a computing device, instructions that cause the computing device to perform operations. The operations include executing, on a processor of a computing device, instructions that cause the computing device to perform operations. The operations include receiving site features associated with a communication site and receiving event features associated with a potential outage-causing event. A classifying engine is employed to generate an impact metric indicating an effect on the communication site from the potential outage-causing event based on the site features and the event features.

Abstract: A matrix multiplication circuit comprises a memory storage device, processing circuitry, a parallel multiply circuit, and buffer circuits. The parallel multiply circuit simultaneously performs a count of multiplies in a parallel multiplication operation. The buffer circuits include prefetch buffer circuits each having a storage array dimension corresponding to the count of multiplies in the parallel multiplication operation. The processing circuitry loads a first prefetch buffer circuit with values from the first matrix; fetches a value of the second matrix and, in parallel with the fetch, preload the second prefetch buffer circuit with another value from the first matrix; initiates a parallel multiply of the fetched value of the second matrix and the values in the first prefetch buffer circuit; and stores partial product results of the parallel multiply, including adding a current partial product result to a previously stored partial product result.

Abstract: A matrix multiplication circuit comprises a memory storage device, processing circuitry, a parallel multiply circuit, and buffer circuits. The parallel multiply circuit simultaneously performs a count of multiplies in a parallel multiplication operation. The buffer circuits include prefetch buffer circuits each having a storage array dimension corresponding to the count of multiplies in the parallel multiplication operation. The processing circuitry loads a first prefetch buffer circuit with values from the first matrix; fetches a value of the second matrix and, in parallel with the fetch, preload the second prefetch buffer circuit with another value from the first matrix; initiates a parallel multiply of the fetched value of the second matrix and the values in the first prefetch buffer circuit; and stores partial product results of the parallel multiply, including adding a current partial product result to a previously stored partial product result.

Abstract: A method includes executing, on a processor of a computing device, instructions that cause the computing device to perform operations. The operations include executing, on a processor of a computing device, instructions that cause the computing device to perform operations. The operations include receiving site features associated with a communication site and receiving event features associated with a potential outage-causing event. A classifying engine is employed to generate an impact metric indicating an effect on the communication site from the potential outage-causing event based on the site features and the event features.