Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract: Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. The circuitry of this of this invention checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage of the invention is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).

Abstract: Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. Run-length detection circuitry checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage offered by the circuitry is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).

Abstract: Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.

Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract: A programmable logic device is configured to accommodate multiplication by the provision in each logic region of specialized components to form and sum partial products. The specialized components are separate from the ordinary logic of the logic region, and their presence imposes little penalty on the performance of ordinary logic functions, while enhancing the speed at which multiplication is performed by minimizing the number of logic regions used for a particular multiplication operation, and also minimizing the use of the interconnection resources of the device to convey signals among those regions.

Abstract: Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

Abstract: Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

Abstract: Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.