Patents by Inventor Vinu K. ELIAS
Vinu K. ELIAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10884476Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.Type: GrantFiled: March 1, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Vinu K. Elias, Sundar Ramani, Arvind S. Tomar, Jianjun Liu
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Patent number: 10481204Abstract: Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.Type: GrantFiled: October 7, 2014Date of Patent: November 19, 2019Assignee: Intel CorporationInventor: Vinu K. Elias
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Publication number: 20190196568Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.Type: ApplicationFiled: March 1, 2019Publication date: June 27, 2019Inventors: Vinu K. Elias, Sundar Ramani, Arvind S. Tomar, Jianjun Liu
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Patent number: 10241556Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.Type: GrantFiled: November 27, 2013Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Vinu K. Elias, Sundar Ramani, Arvind S. Tomar, Jianjun Liu
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Patent number: 10175716Abstract: Technologies for low-power and high-accuracy timestamps are disclosed. A compute device may have a sensor hub to capture sensor data with a corresponding timestamp. In order to save power, the sensor hub may be able to capture sensor data while the compute device is in a standby mode. However, the always running timer of the compute device may not be accessible to the sensor hub while the compute device is in the standby mode. The sensor hub may have a coarse-grained counter and/or fine-grained counter. To correct for any temporal drift, the compute device may determine an error between the always running timer and the coarse-grained and/or fine-grained counters when the compute device is out of the standby mode, and store an indication of the error in a location accessible by the sensor hub, even when the compute device is in the standby mode.Type: GrantFiled: September 29, 2016Date of Patent: January 8, 2019Assignee: Intel CorporationInventor: Vinu K. Elias
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Publication number: 20180224923Abstract: Systems and techniques for lower power key phrase detection are disclosed herein. An audio sample may be captured in a power management integrated circuit (PMIC). Here, the PMIC is physically different than a sensor circuit of an integrated system and the PMIC has a lower power leakage than the sensor circuit. The integrated system may be awoken upon a trigger. The audio sample may then be transferred to the integrated system to perform key phrase detection (KPD). The integrated system may be put to sleep in response to completion of the KPD.Type: ApplicationFiled: February 8, 2017Publication date: August 9, 2018Inventors: Vinu K. Elias, Senaka Cuda Bandara Ratnayake, Paul S. Durley, Moorthy Rajesh, Darren S. Crews
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Publication number: 20180088626Abstract: Technologies for low-power and high-accuracy timestamps are disclosed. A compute device may have a sensor hub to capture sensor data with a corresponding timestamp. In order to save power, the sensor hub may be able to capture sensor data while the compute device is in a standby mode. However, the always running timer of the compute device may not be accessible to the sensor hub while the compute device is in the standby mode. The sensor hub may have a coarse-grained counter and/or fine-grained counter. To correct for any temporal drift, the compute device may determine an error between the always running timer and the coarse-grained and/or fine-grained counters when the compute device is out of the standby mode, and store an indication of the error in a location accessible by the sensor hub, even when the compute device is in the standby mode.Type: ApplicationFiled: September 29, 2016Publication date: March 29, 2018Inventor: Vinu K. Elias
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Patent number: 9552051Abstract: Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal Serial Bus (USB) physical subsystem and system firmware, wherein the system firmware conveys USB related events to the SOC. The system is configured to include a power management apparatus, where the power management apparatus includes USB wake functionality and USB On-the-Go (OTG) functionality.Type: GrantFiled: May 15, 2014Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Vinu K. Elias, Sridharan Ranganathan, Paul S. Durley
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Patent number: 9509292Abstract: Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.Type: GrantFiled: September 29, 2011Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Vinu K. Elias, Chih-Liang Leon Huang
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Publication number: 20160246352Abstract: In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.Type: ApplicationFiled: November 27, 2013Publication date: August 25, 2016Inventors: VINU K. ELIAS, SUNDAR RAMANI, ARVIND S. TOMAR, JIANJUN LIU
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Publication number: 20160241244Abstract: Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.Type: ApplicationFiled: April 21, 2016Publication date: August 18, 2016Inventors: Vinu K. Elias, Chih-Liang Leon Huang
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Publication number: 20150333735Abstract: Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal Serial Bus (USB) physical subsystem and system firmware, wherein the system firmware conveys USB related events to the SOC. The system is configured to include a power management apparatus, where the power management apparatus includes USB wake functionality and USB On-the-Go (OTG) functionality.Type: ApplicationFiled: May 15, 2014Publication date: November 19, 2015Inventors: VINU K. ELIAS, SRIDHARAN RANGANATHAN, PAUL S. DURLEY
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Publication number: 20150025830Abstract: Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement ent circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.Type: ApplicationFiled: October 7, 2014Publication date: January 22, 2015Inventor: VINU K. ELIAS
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Patent number: 8860455Abstract: Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.Type: GrantFiled: December 24, 2010Date of Patent: October 14, 2014Assignee: Intel CorporationInventor: Vinu K. Elias
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Publication number: 20130249603Abstract: Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.Type: ApplicationFiled: September 29, 2011Publication date: September 26, 2013Inventors: Vinu K. Elias, Chih-Liang Leon Huang
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Publication number: 20120161808Abstract: Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.Type: ApplicationFiled: December 24, 2010Publication date: June 28, 2012Inventor: Vinu K. ELIAS