Abstract: A data byte element E located at position d in entry i of memory section M.sub.a having reference entry TR is addressed. Memory section M.sub.a is one section of a table in a data processory memory, such that each of the entries in section M.sub.a has a predetermined number (t) of elements E. Signals having values related to the values of i, t and TR of several memory sections are stored in a storage device and read out when the storage device is addressed. A signal related to the value of d is also derived as a result of read-out from the storage device. The signals having values related to the values of i, t, TR and d are combined to derive an addressing signal for element E in memory section M.sub.a of the table of the data processing memory. An address circuit for the data processing memory responds to the addressing signal to addressing element E in memory section M.sub.a.

Abstract: An arrangement for dynamically translating virtual address into absolute or physical addresses of items of data. Each virtual address includes a segment table number, a segment table entry, and a segment page number. Segment descriptors are stored in a central memory. The address of a particular segment descriptor may be calculated from the segment table number and the segment table entry. From the segment descriptor, a unique identification termed a logic page number may be calculated. The logic page number permits pseudo-associative access to a table containing a number of entries proportional to the number of physical pages of the main memory, allowing the physical address to be determined.