Abstract: The peak power requirements for operations performed on a FLASH memory circuit vary substantially, with reading, writing and erasing requiring increasing levels of power. When the memory is operated to improve performance using erase hiding, the performance of write or erase operations where the time periods for such operations can overlap results in increased peak power requirements. Controlling the time periods during which modules of a RAID group are permitted to perform erase operations, with respect to other modules in other RAID groups may smooth out the requirements. In addition, such scheduling may lead to improved efficiency in using shared data buses.