Patents by Inventor Viorel C. Ontalus
Viorel C. Ontalus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11728380Abstract: Aspects of the disclosure provide a bipolar transistor structure with a sub-collector on a substrate, a first collector region on a first portion of the sub-collector, a trench isolation (TI) on a second portion of the sub-collector and adjacent the first collector region, and a second collector region on a third portion of the sub-collector and adjacent the TI. A base on first collector region and a portion of the TI. An emitter is on a first portion of the base above the first collector region. The base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.Type: GrantFiled: June 24, 2021Date of Patent: August 15, 2023Assignee: GlobalFoundries U.S. Inc.Inventor: Viorel C. Ontalus
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Patent number: 11588043Abstract: Aspects of the disclosure provide a bipolar transistor structure with an elevated extrinsic base, and related methods to form the same. A bipolar transistor according to the disclosure may include a collector on a substrate, and a base film on the collector. The base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region. An emitter is on a first portion of the crystalline region of the base film. An elevated extrinsic base is on a second portion of the crystalline region of the base film, and adjacent the emitter.Type: GrantFiled: April 14, 2021Date of Patent: February 21, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Viorel C. Ontalus, Judson R. Holt
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Publication number: 20220416029Abstract: Aspects of the disclosure provide a bipolar transistor structure with a sub-collector on a substrate, a first collector region on a first portion of the sub-collector, a trench isolation (TI) on a second portion of the sub-collector and adjacent the first collector region, and a second collector region on a third portion of the sub-collector and adjacent the TI. A base on first collector region and a portion of the TI. An emitter is on a first portion of the base above the first collector region. The base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventor: Viorel C. Ontalus
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Publication number: 20220336646Abstract: Aspects of the disclosure provide a bipolar transistor structure with an elevated extrinsic base, and related methods to form the same. A bipolar transistor according to the disclosure may include a collector on a substrate, and a base film on the collector. The base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region. An emitter is on a first portion of the crystalline region of the base film. An elevated extrinsic base is on a second portion of the crystalline region of the base film, and adjacent the emitter.Type: ApplicationFiled: April 14, 2021Publication date: October 20, 2022Inventors: Viorel C. Ontalus, Judson R. Holt
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Patent number: 11404563Abstract: Embodiments of the disclosure provide an insulated-gate bipolar transistor (IGBT), including: a substrate with a first type of doping; a drift region including a first semiconductor material and a second semiconductor material having dissimilar band gaps, the drift region having a second type of doping; and a base region with the first type of doping, wherein the drift region is disposed between the substrate and the base region; wherein a stoichiometry ratio of the first and second semiconductor materials of the drift region varies as a function of distance within the drift region to provide a built-in electric field via band gap modulation. The built-in electric field reduces a band gap barrier for minority charge carriers and increases a drift velocity of the minority charge carriers in the drift region, increasing a frequency response of the IGBT.Type: GrantFiled: December 27, 2019Date of Patent: August 2, 2022Assignee: GlobalFoundries U.S. Inc.Inventor: Viorel C. Ontalus
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Publication number: 20210202722Abstract: Embodiments of the disclosure provide an insulated-gate bipolar transistor (IGBT), including: a substrate with a first type of doping; a drift region including a first semiconductor material and a second semiconductor material having dissimilar band gaps, the drift region having a second type of doping; and a base region with the first type of doping, wherein the drift region is disposed between the substrate and the base region; wherein a stoichiometry ratio of the first and second semiconductor materials of the drift region varies as a function of distance within the drift region to provide a built-in electric field via band gap modulation. The built-in electric field reduces a band gap barrier for minority charge carriers and increases a drift velocity of the minority charge carriers in the drift region, increasing a frequency response of the IGBT.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventor: Viorel C. Ontalus
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Publication number: 20180108654Abstract: A method of forming a FinFET device includes ion implanting a diffusion-inhibiting species such as carbon into source and drain regions of a semiconductor fin prior to a dopant activating anneal. The implanted carbon, which can be incorporated into the fin in conjunction with a replacement metal gate process after defining a sacrificial gate but prior to forming sidewall spacers on the gate, forms a barrier that impedes dopant diffusion across the barrier, which enables abrupt junctions and higher overall dopant concentrations within the semiconductor fin.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Applicant: GLOBALFOUNDRIES, INC.Inventors: Viorel C. ONTALUS, Arvind KUMAR, Xin WANG, Gan WANG
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Patent number: 9673295Abstract: A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.Type: GrantFiled: May 27, 2014Date of Patent: June 6, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Annie Levesque, Viorel C. Ontalus, Matthew W. Stoker
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Patent number: 9293593Abstract: A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.Type: GrantFiled: May 17, 2012Date of Patent: March 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Judson R. Holt, Viorel C. Ontalus, Keith H. Tabakman
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Publication number: 20150349068Abstract: A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.Type: ApplicationFiled: May 27, 2014Publication date: December 3, 2015Applicant: International Business Machines CorporationInventors: Annie Levesque, Viorel C. Ontalus, Matthew W. Stoker
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Patent number: 9059285Abstract: A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS including: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT).Type: GrantFiled: February 20, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Viorel C. Ontalus
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Patent number: 9059286Abstract: A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.Type: GrantFiled: March 31, 2014Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Judson R. Holt, Viorel C. Ontalus, Keith H. Tabakman
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Patent number: 9013008Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.Type: GrantFiled: October 11, 2013Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Xi Li, Viorel C. Ontalus
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Patent number: 9006052Abstract: A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.Type: GrantFiled: October 11, 2010Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Judson R. Holt, Viorel C. Ontalus, Keith H. Tabakman
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Patent number: 8921939Abstract: A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.Type: GrantFiled: January 28, 2013Date of Patent: December 30, 2014Assignee: International Business Machines CorporationInventors: Jeffrey B. Johnson, Ramachandran Muralidhar, Philip J. Oldiges, Viorel C. Ontalus, Kai Xiu
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Publication number: 20140213029Abstract: A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: International Business Machines CorporationInventors: Judson R. Holt, Viorel C. Ontalus, Keith H. Tabakman
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Patent number: 8779525Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.Type: GrantFiled: February 21, 2013Date of Patent: July 15, 2014Assignees: International Business Machines Corporation, GlobalFoundries, IncInventors: Bo Bai, Linda Black, Abhishek Dube, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman
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Publication number: 20140034970Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.Type: ApplicationFiled: October 11, 2013Publication date: February 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xi LI, Viorel C. ONTALUS
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Patent number: 8618617Abstract: A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.Type: GrantFiled: March 4, 2013Date of Patent: December 31, 2013Assignees: International Business Machines Corporation, GlobalFoundries, Inc.Inventors: Kevin K. Chan, Abhishek Dube, Eric C. Harley, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman, Linda R. Black
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Patent number: 8604564Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.Type: GrantFiled: March 16, 2012Date of Patent: December 10, 2013Assignee: International Business Machine CorporationInventors: Xi Li, Viorel C. Ontalus