Abstract: Aspects of the disclosure provide a bipolar transistor structure with a sub-collector on a substrate, a first collector region on a first portion of the sub-collector, a trench isolation (TI) on a second portion of the sub-collector and adjacent the first collector region, and a second collector region on a third portion of the sub-collector and adjacent the TI. A base on first collector region and a portion of the TI. An emitter is on a first portion of the base above the first collector region. The base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.

Abstract: Aspects of the disclosure provide a bipolar transistor structure with an elevated extrinsic base, and related methods to form the same. A bipolar transistor according to the disclosure may include a collector on a substrate, and a base film on the collector. The base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region. An emitter is on a first portion of the crystalline region of the base film. An elevated extrinsic base is on a second portion of the crystalline region of the base film, and adjacent the emitter.

Abstract: Aspects of the disclosure provide a bipolar transistor structure with a sub-collector on a substrate, a first collector region on a first portion of the sub-collector, a trench isolation (TI) on a second portion of the sub-collector and adjacent the first collector region, and a second collector region on a third portion of the sub-collector and adjacent the TI. A base on first collector region and a portion of the TI. An emitter is on a first portion of the base above the first collector region. The base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.

Abstract: Aspects of the disclosure provide a bipolar transistor structure with an elevated extrinsic base, and related methods to form the same. A bipolar transistor according to the disclosure may include a collector on a substrate, and a base film on the collector. The base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region. An emitter is on a first portion of the crystalline region of the base film. An elevated extrinsic base is on a second portion of the crystalline region of the base film, and adjacent the emitter.

Abstract: Embodiments of the disclosure provide an insulated-gate bipolar transistor (IGBT), including: a substrate with a first type of doping; a drift region including a first semiconductor material and a second semiconductor material having dissimilar band gaps, the drift region having a second type of doping; and a base region with the first type of doping, wherein the drift region is disposed between the substrate and the base region; wherein a stoichiometry ratio of the first and second semiconductor materials of the drift region varies as a function of distance within the drift region to provide a built-in electric field via band gap modulation. The built-in electric field reduces a band gap barrier for minority charge carriers and increases a drift velocity of the minority charge carriers in the drift region, increasing a frequency response of the IGBT.

Abstract: Embodiments of the disclosure provide an insulated-gate bipolar transistor (IGBT), including: a substrate with a first type of doping; a drift region including a first semiconductor material and a second semiconductor material having dissimilar band gaps, the drift region having a second type of doping; and a base region with the first type of doping, wherein the drift region is disposed between the substrate and the base region; wherein a stoichiometry ratio of the first and second semiconductor materials of the drift region varies as a function of distance within the drift region to provide a built-in electric field via band gap modulation. The built-in electric field reduces a band gap barrier for minority charge carriers and increases a drift velocity of the minority charge carriers in the drift region, increasing a frequency response of the IGBT.

Abstract: A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.

Abstract: A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.

Abstract: A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.

Abstract: A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.

Abstract: A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS including: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT).

Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Abstract: A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.

Abstract: A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.

Abstract: A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.

Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

Abstract: A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.

Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Abstract: A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.

Abstract: A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.