Patents by Inventor Vipin N. Patel

Vipin N. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4560422
    Abstract: A method for fabricating polysilicon of reduced resistance that may be incorporated in silicon integrated chip manufacturing processes which comprises coating a wafer bearing dielectrically isolated islands with an isolating layer, and depositing thereover a layer of polysilicon. On the surface of the polysilicon layer, a masking layer is formed, and coated with a metallic reflective layer. The portion of the reflective layer, and, optionally, the masking layer, overlaying the interisland area is removed, and the wafer is then exposed to a laser beam, transforming the polysilicon layer into the appropriate resistor material. The remaining metallic and/or masking layer may then be removed, the device exposed to a laser beam again, thereby transforming the polysilicon across the entire surface.
    Type: Grant
    Filed: June 21, 1984
    Date of Patent: December 24, 1985
    Assignee: Harris Corporation
    Inventor: Vipin N. Patel
  • Patent number: 4475955
    Abstract: A method for fabricating polysilicon of reduced resistance that may be incorporated in silicon integrated chip manufacturing processes which comprises coating a wafer bearing dielectrically isolated islands with an isolating layer, and depositing thereover a layer of polysilicon. On the surface of the polysilicon layer, a masking layer is formed, and coated with a metallic reflective layer. The portion of the reflective layer, and, optionally, the masking layer, overlaying the interisland area is removed, and the wafer is then exposed to a laser beam, transforming the polysilicon layer into the appropriate resistor material. The remaining metallic and/or masking layer may then be removed, the device exposed to a laser beam again, thereby transforming the polysilicon across the entire surface.
    Type: Grant
    Filed: December 6, 1982
    Date of Patent: October 9, 1984
    Assignee: Harris Corporation
    Inventor: Vipin N. Patel
  • Patent number: 4433342
    Abstract: A residual crystallization retardation layer is provided between the non-crystalline switchable semiconductor layer and each electrode structure. Amorphous germanium, silicon or carbon form good crystallization retardation layers and also minimize electromigration and reduce solubility of tellurium in the electrodes.
    Type: Grant
    Filed: April 6, 1981
    Date of Patent: February 21, 1984
    Assignee: Harris Corporation
    Inventors: Vipin N. Patel, John L. Conarroe, Jr.
  • Patent number: 4389713
    Abstract: A first voltage pulse is applied having sufficient amplitude to switch the device from a high to a low resistance state and subsequently maintaining a holding current. A second voltage pulse is applied after the device has switched to drive the filamentous path into the liquid phase for a short duration.
    Type: Grant
    Filed: June 10, 1981
    Date of Patent: June 21, 1983
    Assignee: Harris Corporation
    Inventors: Vipin N. Patel, Joseph S. Raby