Patents by Inventor Vipin Pandey

Vipin Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Amorphous form of lomitapide mesylate
    Patent number: 10138206
    Abstract: Provided is novel amorphous form of lomitapide mesylate salt and process for preparation thereof.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: November 27, 2018
    Assignee: GLENMARK PHARMACEUTICALS LIMITED
    Inventors: Shekhar Bhaskar Bhirud, Samir Naik, Sushanta Mishra, Vipin Pandey, Deepak S. Patekar
  • AMORPHOUS FORM OF LOMITAPIDE MESYLATE
    Publication number: 20170305858
    Abstract: Provided is novel amorphous form of lomitapide mesylate salt and process for preparation thereof.
    Type: Application
    Filed: October 6, 2015
    Publication date: October 26, 2017
    Inventors: Shekhar Bhaskar BHIRUD, Samir NAIK, Sushanta MISHRA, Vipin PANDEY, Deepak S. PATEKAR
  • Integrated circuit design timing path verification tool
    Patent number: 9305125
    Abstract: An EDA tool for validating predefined timing paths having corresponding timing constraints in an integrated circuit (IC) design has a processor that performs a static-timing-analysis (STA) of the IC design and generates a STA report that includes the first set of timing constraints, which include a first number of clock cycles required for propagating the first multi-cycle timing path. A simulation-based checker based on a STA that counts a second number of clock cycles that is actually required by the first multi-cycle timing path to propagate is generated while performing a unit-delay, gate-level netlist simulation of the first-multiple cycle timing path. The first set of timing constraints then are modified so that the first multi-cycle timing path is redefined to require the second number of clock cycles to propagate.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: April 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vipin Pandey, Sidhartha Taneja
  • INTEGRATED CIRCUIT DESIGN TIMING PATH VERIFICATION TOOL
    Publication number: 20150248513
    Abstract: An EDA tool for validating predefined timing paths having corresponding timing constraints in an integrated circuit (IC) design has a processor that performs a static-timing-analysis (STA) of the IC design and generates a STA report that includes the first set of timing constraints, which include a first number of clock cycles required for propagating the first multi-cycle timing path. A simulation-based checker based on a STA that counts a second number of clock cycles that is actually required by the first multi-cycle timing path to propagate is generated while performing a unit-delay, gate-level netlist simulation of the first-multiple cycle timing path. The first set of timing constraints then are modified so that the first multi-cycle timing path is redefined to require the second number of clock cycles to propagate.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Inventors: Vipin Pandey, Sidhartha Taneja