Patents by Inventor Vipin S. Boyanapalli

Vipin S. Boyanapalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficient method and apparatus for low latency forward error correction
    Patent number: 7007223
    Abstract: A method and apparatus for low latency Forward Error Correction (FEC) is described. The low latency FEC can be implemented utilizing shift registers, at least one Linear Feedback Shift Register (LFSR), and a local reference table.
    Type: Grant
    Filed: June 30, 2002
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventor: Vipin S. Boyanapalli
  • Efficient method and apparatus for low latency forward error correction
    Publication number: 20040003334
    Abstract: A method and apparatus for low latency Forward Error Correction (FEC) is described. The low latency FEC can be implemented utilizing shift registers, at least one Linear Feedback Shift Register (LFSR), and a local reference table.
    Type: Application
    Filed: June 30, 2002
    Publication date: January 1, 2004
    Inventor: Vipin S. Boyanapalli