Patents by Inventor Vipul Anil Desai

Vipul Anil Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7027531
    Abstract: A method for processing an information sequence with an iterative decoder is provided. The information sequence is divided into a current window and at least one additional window. The current window of the information sequence is selected. At least one metric value for a current recursion of the current window is computed based on metric values from the additional window of the information sequence, wherein the additional window is a past iteration. Systems and programs for processing an information sequence are also provided.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: April 11, 2006
    Assignee: Motorola, Inc.
    Inventors: Thomas Keith Blankenship, Brian Keith Classon, Vipul Anil Desai
  • Patent number: 6971056
    Abstract: System (100) for generating syndrome (222) usable in decoder (130) includes reducer (340) and converter (330). Reducer (340) employs information to generate representation (342). Converter (330) generates, with employment of representation (342), syndrome (222).
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: November 29, 2005
    Assignee: Motorola, Inc.
    Inventors: Brian Keith Classon, Vipul Anil Desai
  • Patent number: 6952457
    Abstract: A method of processing an information sequence with a decoder is provided. A window within the information sequence is selected. A training period is calculated for the window. At least one recursion of the window is initialized based on the calculated training period. Systems and programs for processing the information sequence are also provided.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: October 4, 2005
    Assignee: Motorola, Inc.
    Inventors: Thomas Keith Blankenship, Brian Keith Classon, Vipul Anil Desai
  • Patent number: 6922716
    Abstract: A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and second vector arithmetic logic unit wherein the first register file has a first plurality of cross connections to the second vector arithmetic logic unit; wherein the second register file as a second plurality of cross connections to the first vector arithmetic logic unit.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: July 26, 2005
    Assignee: Motorola, Inc.
    Inventors: Vipul Anil Desai, David P. Gurney, Benson Chau
  • Patent number: 6769091
    Abstract: A squished trellis encoder encodes blocks of information with unequal error correction. A multiplexing switch partitions the information block into a first portion and a second portion. A first trellis encoder encodes the first portion. A second trellis encoder encodes the second portion. An initial state information generator maps the states of the first trellis encoder to the second trellis encoder to establish initial conditions for the states of the second trellis encoder. A delay delays the second portion from processing by the second trellis encoder until the initial state information generator has mapped the states. An associated decoder can use the novel squished approach or other alternative approaches.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: July 27, 2004
    Assignee: Motorola, Inc.
    Inventors: Brian Classon, Vipul Anil Desai, John Johnson, Yufei Wu Blankenship
  • Patent number: 6760390
    Abstract: The log-add kernel operation is represented as a summation of an average and a correction factor composed of a constant and a term based on a difference between the input arguments. In a described embodiment, the correction factor is approximated using the reduction of the correction factor into a Taylor series expansion, which may be defined around the difference between the input arguments as approximately zero. The approach may be further optimized to provide the Taylor series expansion as being modified to compute the correction factor with simple additions, multiplications, and shift operations. If the input arguments are close to each other, the new computed representation may be used, and if the arguments are further apart, the max operation is used. The log-add kernel operation also may be extended to more than two arguments, for application, for example, in the kernel operation of the generalized Viterbi decoder with a branch fan-in greater than 2.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: July 6, 2004
    Assignee: Motorola, Inc.
    Inventors: Vipul Anil Desai, Brian Keith Classon, Thomas Keith Blankenship
  • Patent number: 6745315
    Abstract: Controller component (155) of system (100) generates address pattern (902) through employment of one or more parameters (205), to store information (810) at a plurality of parts of storage, for example, one or more instances of banked data memory (140) that are employable with multiprocessing. The one or more parameters (205) are related to the information (810).
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: June 1, 2004
    Assignee: Motorola Inc.
    Inventors: David P. Gurney, Vipul Anil Desai
  • Patent number: 6700867
    Abstract: The invention provides a method for operating a hybrid automatic repeat request communication system wherein it is determined whether a receiver can process a data packet, and a self-decode request associated with the data packet is sent based on the determination.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: March 2, 2004
    Assignee: Motorola, Inc.
    Inventors: Brian Keith Classon, Vipul Anil Desai, Mark Cudak
  • Publication number: 20030167460
    Abstract: A plurality of compound Single Instruction/Multiple Data instructions in the form of vector arithmetic unit instructions and vector network unit instructions are disclosed. Each compound Single Instruction/Multiple Data instruction is formed by a selection of two or more Single Instruction/Multiple Data operations of a reduced instruction set computing type, and a combination of the selected Single Instruction/Multiple Data operations to execute in a single instruction cycle to thereby yield the compound Single Instruction/Multiple Data instruction.
    Type: Application
    Filed: February 26, 2002
    Publication date: September 4, 2003
    Inventors: Vipul Anil Desai, David P. Gurney, Benson Chau, Kevin M. Cutts
  • Publication number: 20030118031
    Abstract: The invention provides a method for operating a hybrid automatic repeat request communication system wherein it is determined whether a receiver can process a data packet, and a self-decode request associated with the data packet is sent based on the determination.
    Type: Application
    Filed: December 20, 2001
    Publication date: June 26, 2003
    Inventors: Brian Keith Classon, Vipul Anil Desai, Mark Cudak
  • Publication number: 20030037218
    Abstract: Controller component (155) of system (100) generates address pattern (902) through employment of one or more parameters (205), to store information (810) at a plurality of parts of storage, for example, one or more instances of banked data memory (140) that are employable with multiprocessing. The one or more parameters (205) are related to the information (810).
    Type: Application
    Filed: August 14, 2001
    Publication date: February 20, 2003
    Inventors: David P. Gurney, Vipul Anil Desai
  • Publication number: 20020124224
    Abstract: A method of preparing an information sequence before encoding is provided. An information sequence size of the information sequence is compared to an interleaver size of an interleaver. At least one symbol is added to the information sequence to match the information sequence size to the interleaver size. Systems and programs for preparing an information sequence before encoding are also provided.
    Type: Application
    Filed: October 2, 2001
    Publication date: September 5, 2002
    Inventors: Thomas Keith Blankenship, Brian Keith Classon, Vipul Anil Desai
  • Publication number: 20020118776
    Abstract: A method of processing an information sequence with a decoder is provided. A window within the information sequence is selected. A training period is calculated for the window. At least one recursion of the window is initialized based on the calculated training period. Systems and programs for processing the information sequence are also provided.
    Type: Application
    Filed: October 10, 2001
    Publication date: August 29, 2002
    Inventors: Thomas Keith Blankenship, Brian Keith Classon, Vipul Anil Desai
  • Publication number: 20020118777
    Abstract: A method for processing an information sequence with an iterative decoder is provided. The information sequence is divided into a current window and at least one additional window. The current window of the information sequence is selected. At least one metric value for a current recursion of the current window is computed based on metric values from the additional window of the information sequence, wherein the additional window is a past iteration. Systems and programs for processing an information sequence are also provided.
    Type: Application
    Filed: October 11, 2001
    Publication date: August 29, 2002
    Inventors: Thomas Keith Blankenship, Brian Keith Classon, Vipul Anil Desai
  • Publication number: 20020066061
    Abstract: A squished trellis encoder encodes blocks of information with unequal error correction. A multiplexing switch (220) partitions the information block into a first portion and a second portion. A first trellis encoder (261) encodes the first portion. A second trellis encoder (263) encodes the second portion. An initial state information generator (265) maps the states of the first trellis encoder to the second trellis encoder to establish initial conditions for the states of the second trellis encoder. A delay (255) delays the second portion from processing by the second trellis encoder until the initial state information generator has mapped the states. An associated decoder can use the novel squished approach (310, 330, 340) or other alternative approaches.
    Type: Application
    Filed: October 17, 2001
    Publication date: May 30, 2002
    Inventors: Brian Classon, Vipul Anil Desai, John Johnson, Yufei Wu Blankenship