Patents by Inventor Vipul KUMAR SINGHAL
Vipul KUMAR SINGHAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11190105Abstract: An electronic device having multiple power output circuits that individually include a switch control input, a bypass control input, an output transistor and an output control circuit that includes an RC circuit with a resistor and a capacitor coupled to the output transistor gate and a bypass switch in parallel with the RC circuit resistor. The electronic device includes a controller that selects one of the power output circuits for a given power transfer cycle, closes the bypass switch to bypass the resistor of the selected power output circuit and turns the output transistor of the selected power output circuit on to transfer current from the inductor to a load of the selected power output circuit.Type: GrantFiled: December 11, 2020Date of Patent: November 30, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vipul Kumar Singhal, RR Manikandan, Rajat Chauhan, Vinod Joseph Menezes
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Patent number: 10855184Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: GrantFiled: October 14, 2019Date of Patent: December 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vinod Joseph Menezes, Manikandan Rr, Rajat Chauhan, Vipul Kumar Singhal, Mahesh Madhukar Mehendale, Kaichien Tsai
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Publication number: 20200204075Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: ApplicationFiled: October 14, 2019Publication date: June 25, 2020Inventors: Vinod Joseph MENEZES, Manikandan RR, Rajat CHAUHAN, Vipul Kumar SINGHAL, Mahesh Madhukar MEHENDALE, Kaichien TSAI
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Patent number: 10601408Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.Type: GrantFiled: April 13, 2018Date of Patent: March 24, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajat Chauhan, Vipul Kumar Singhal, Vinod Joseph Menezes, Mahesh Madhukar Mehendale
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Publication number: 20190319614Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.Type: ApplicationFiled: April 13, 2018Publication date: October 17, 2019Inventors: Rajat Chauhan, Vipul Kumar Singhal, Vinod Joseph Menezes, Mahesh Madhukar Mehendale
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Patent number: 10447142Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: GrantFiled: December 20, 2018Date of Patent: October 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vinod Joseph Menezes, Manikandan RR, Rajat Chauhan, Vipul Kumar Singhal, Mahesh Madhukar Mehendale, Kaichien Tsai
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Patent number: 10432192Abstract: A circuit includes an input stage that includes a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device. A compensation stage includes a second transistor device coupled with a third transistor device. The second transistor device is activated in response to the first output signal exceeding a second threshold voltage of the second transistor device. The third transistor device is activated in response to activation of the second transistor device and a second bias current. The compensation stage is configured to generate a second output signal in response to the activation of the third transistor device. An output stage is configured to generate a reset signal in response to the second output signal exceeding a third threshold voltage.Type: GrantFiled: August 23, 2018Date of Patent: October 1, 2019Assignee: Texas Instruments IncorporatedInventors: Divya Kaur, Rajat Chauhan, Vipul Kumar Singhal
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Patent number: 9812960Abstract: Methods and apparatus for DC-DC power controller with low standby current and fast transient response. In an example arrangement, an apparatus includes a voltage converter outputting a direct current output voltage, configured to increase the output voltage responsive to an enable control signal; at least one feedback comparator configured to output a first control signal, the feedback comparator being active responsive to an edge at a clock signal input; an adjustable frequency oscillator for outputting a first clock signal; and a fast transient detect circuit configured to output a second signal asynchronously upon detecting a rapid change greater than a voltage threshold in the output voltage; the voltage converter receiving the enable control signal when either the first clock signal is active, or the second signal is active and the output voltage is less than a reference voltage. Additional apparatus and methods are disclosed.Type: GrantFiled: December 29, 2015Date of Patent: November 7, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Keith Edmund Kunz, Vipul Kumar Singhal, Rajat Chauhan, Per Torstein Røine, Danielle Griffith
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Publication number: 20170187286Abstract: Methods and apparatus for DC-DC power controller with low standby current and fast transient response. In an example arrangement, an apparatus includes a voltage converter outputting a direct current output voltage, configured to increase the output voltage responsive to an enable control signal; at least one feedback comparator configured to output a first control signal, the feedback comparator being active responsive to an edge at a clock signal input; an adjustable frequency oscillator for outputting a first clock signal; and a fast transient detect circuit configured to output a second signal asynchronously upon detecting a rapid change greater than a voltage threshold in the output voltage; the voltage converter receiving the enable control signal when either the first clock signal is active, or the second signal is active and the output voltage is less than a reference voltage. Additional apparatus and methods are disclosed.Type: ApplicationFiled: December 29, 2015Publication date: June 29, 2017Inventors: Keith Edmund Kunz, Vipul Kumar Singhal, Rajat Chauhan, Per Torstein Røine, Danielle Griffith
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Patent number: 9692416Abstract: A buffer that drives components during a standby mode includes a first combination of two standard voltage threshold (SVT) transistors and two high voltage threshold (HVT) transistors that generate a logic 1 signal at a first output. A second combination of two SVT transistors and two HVT transistors generates a logic 0 signal at a second output. A power supply operates the buffer, wherein the power supply generates a voltage less that the threshold voltages of the HVT transistors.Type: GrantFiled: March 21, 2016Date of Patent: June 27, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vipul Kumar Singhal
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Patent number: 9287858Abstract: Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.Type: GrantFiled: October 23, 2014Date of Patent: March 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vipul Kumar Singhal
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Publication number: 20160071849Abstract: A complementary metal oxide semiconductor (CMOS) device having an active mode and a standby mode. The CMOS device includes a first transistor having a first body, a second transistor having a second body, a first forward body bias voltage source, and a second forward body bias voltage source. The first forward body bias voltage source is coupled to the first body when the CMOS device is in the active mode, and is disconnected from the first body when the CMOS device is in the standby mode. The second forward body bias voltage source is coupled to the second body when the CMOS device is in the active mode, and is disconnected from the second body when the CMOS device is in the standby mode.Type: ApplicationFiled: February 17, 2015Publication date: March 10, 2016Inventor: Vipul Kumar Singhal
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Publication number: 20160065188Abstract: Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.Type: ApplicationFiled: October 23, 2014Publication date: March 3, 2016Applicant: Texas Instruments IncorporatedInventor: Vipul Kumar Singhal
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Patent number: 9276566Abstract: A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For example, a first latch can be used to latch a first state of an input to a flip-flop in response to a first (e.g., positive-going) edge of a clock signal and a second latch can be used to latch a second state of the input to the flip-flop in response to a second (e.g., negative-going) edge of a clock signal. A retention latch can be used to latch and retain the state of the flip-flop when the first and second latches are disabled to save power in the low-power mode. The retention latch can also be used to initialize at least one of the first and second flip-flops when exiting the low-power mode.Type: GrantFiled: August 26, 2014Date of Patent: March 1, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Vipul Kumar Singhal
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Publication number: 20150188519Abstract: A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For example, a first latch can be used to latch a first state of an input to a flip-flop in response to a first (e.g., positive-going) edge of a clock signal and a second latch can be used to latch a second state of the input to the flip-flop in response to a second (e.g., negative-going) edge of a clock signal. A retention latch can be used to latch and retain the state of the flip-flop when the first and second latches are disabled to save power in the low-power mode. The retention latch can also be used to initialize at least one of the first and second flip-flops when exiting the low-power mode.Type: ApplicationFiled: August 26, 2014Publication date: July 2, 2015Inventor: Vipul KUMAR SINGHAL