Patents by Inventor Vipul MEHTA
Vipul MEHTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240402445Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 8, 2024Publication date: December 5, 2024Inventors: Bassam ZIADEH, Jingyi HUANG, Yiqun BAI, Ziyin LIN, Vipul MEHTA, Joseph VAN NAUSDLE
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Patent number: 12130482Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.Type: GrantFiled: December 23, 2020Date of Patent: October 29, 2024Assignee: Intel CorporationInventors: Bassam Ziadeh, Jingyi Huang, Yiqun Bai, Ziyin Lin, Vipul Mehta, Joseph Van Nausdle
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Publication number: 20240258183Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.Type: ApplicationFiled: April 10, 2024Publication date: August 1, 2024Inventors: Edvin CETEGEN, Jacob VEHONSKY, Nicholas S. HAEHN, Thomas HEATON, Steve S. CHO, Rahul JAIN, Tarek IBRAHIM, Antariksh Rao Pratap SINGH, Nicholas NEAL, Sergio CHAN ARGUEDAS, Vipul MEHTA
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Patent number: 12009271Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.Type: GrantFiled: July 15, 2019Date of Patent: June 11, 2024Assignee: Intel CorporationInventors: Edvin Cetegen, Jacob Vehonsky, Nicholas S. Haehn, Thomas Heaton, Steve S. Cho, Rahul Jain, Tarek Ibrahim, Antariksh Rao Pratap Singh, Nicholas Neal, Sergio Chan Arguedas, Vipul Mehta
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Patent number: 12002727Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.Type: GrantFiled: February 11, 2020Date of Patent: June 4, 2024Assignee: Intel CorporationInventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
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Publication number: 20240153837Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die, and an array of pillars adjacent to the die. In an embodiment, the electronic package further comprises an underfill under the die, where an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and where the edge of the underfill has a height that is less than a maximum height of the underfill.Type: ApplicationFiled: November 8, 2022Publication date: May 9, 2024Inventors: Ziyin LIN, Vipul MEHTA, Jonas CROISSANT, Jigneshkumar PATEL, Dingying XU, Gang DUAN, Aditya Sumanth YERRAMILLI, Suriyakala RAMALINGAM, Xavier BRUN
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Patent number: 11776821Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.Type: GrantFiled: February 10, 2022Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
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Patent number: 11749585Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.Type: GrantFiled: February 28, 2020Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Yiqun Bai, Vipul Mehta, John Decker, Ziyin Lin
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Patent number: 11688634Abstract: Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.Type: GrantFiled: July 30, 2019Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Vipul Mehta, Yiqun Bai, Ziyin Lin, John Decker, Yan Li
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Patent number: 11676876Abstract: A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material.Type: GrantFiled: August 30, 2019Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Ziyin Lin, Elizabeth Nofen, Vipul Mehta, Taylor Gaines
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Patent number: 11379798Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for surfacing content related to electronic calendar events are presented. An electronic calendar event library may be maintained. One or more calendar events that meet threshold time criteria in relation to a current time may be identified. One or more rules may be applied to the identified events to determine whether contextual information and/or actions should be surfaced in relation to those events. In some examples, an event priority score may be calculated for each of the identified events. Contextual information and/or actions associated with events with event priority scores that exceed a threshold value may be surfaced. The contextual information and/or actions may be prioritized based on the event priority scores.Type: GrantFiled: May 28, 2020Date of Patent: July 5, 2022Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Christopher Shingee Park, Siddhant Vipul Mehta, Daniel Steven Leclair
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Publication number: 20220196937Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Bassam ZIADEH, Jingyi HUANG, Yiqun BAI, Ziyin LIN, Vipul MEHTA, Joseph VAN NAUSDLE
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Publication number: 20220165585Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.Type: ApplicationFiled: February 10, 2022Publication date: May 26, 2022Inventors: Ziyin LIN, Vipul MEHTA, Edvin CETEGEN, Yuying WEI, Sushrutha GUJJULA, Nisha ANANTHAKRISHNAN, Shan ZHONG
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Patent number: 11282717Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.Type: GrantFiled: March 30, 2018Date of Patent: March 22, 2022Assignee: Intel CorporationInventors: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
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Patent number: 11193846Abstract: A compressible element for a sensor assembly includes an elastomer matrix having a first compressibility and a plurality of closed areas distributed within the elastomer matrix and each surrounded by the elastomer matrix. Each of the closed areas has a second compressibility greater than the first compressibility.Type: GrantFiled: March 16, 2020Date of Patent: December 7, 2021Assignees: TE CONNECTIVITY SERVICES GMBH, MEASUREMENT SPECIALTIES, INC.Inventors: Megan Hoarfrost Beers, Miguel Morales, Vishrut Vipul Mehta, Yilang Wu, Ting Gao, Vincent Wong, Jonathan Tran, Natasha V. Kachenko
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Publication number: 20210374683Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for surfacing content related to electronic calendar events are presented. An electronic calendar event library may be maintained. One or more calendar events that meet threshold time criteria in relation to a current time may be identified. One or more rules may be applied to the identified events to determine whether contextual information and/or actions should be surfaced in relation to those events. In some examples, an event priority score may be calculated for each of the identified events. Contextual information and/or actions associated with events with event priority scores that exceed a threshold value may be surfaced. The contextual information and/or actions may be prioritized based on the event priority scores.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: Christopher Shingee Park, Siddhant Vipul Mehta, Daniel Steven Leclair
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Publication number: 20210285837Abstract: A compressible element for a sensor assembly includes an elastomer matrix having a first compressibility and a plurality of closed areas distributed within the elastomer matrix and each surrounded by the elastomer matrix. Each of the closed areas has a second compressibility greater than the first compressibility.Type: ApplicationFiled: March 16, 2020Publication date: September 16, 2021Applicants: TE Connectivity Services GmbH, Measurement Specialities, Inc.Inventors: Megan Hoarfrost Beers, Miguel Morales, Vishrut Vipul Mehta, Yilang Wu, Ting Gao, Vincent Wong, Jonathan Tran, Natasha V. Kachenko
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Publication number: 20210272878Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Applicant: Intel CorporationInventors: Yiqun Bai, Vipul Mehta, John Decker, Ziyin Lin
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Publication number: 20210249322Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Applicant: Intel CorporationInventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
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Publication number: 20210066162Abstract: A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.Type: ApplicationFiled: August 30, 2019Publication date: March 4, 2021Inventors: Sergio A. CHAN ARGUEDAS, Nicholas S. HAEHN, Edvin CETEGEN, Nicholas NEAL, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON, Vipul MEHTA