Patents by Inventor Vipul Parikh

Vipul Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9633159
    Abstract: Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 25, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vipul Parikh, Lalit Bharat, Shagufta Siddique, Prashant Sethia, Naresh Kumar
  • Patent number: 7146303
    Abstract: A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: December 5, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Aninda Roy, Vipul Parikh
  • Publication number: 20040172232
    Abstract: A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Inventors: Aninda Roy, Vipul Parikh
  • Patent number: 6691082
    Abstract: A system and method are provided for processing audio and speech signals using a pitch and voicing dependent spectral estimation algorithm (voicing algorithm) to accurately represent voiced speech, unvoiced speech, and mixed speech in the presence of background noise, and background noise with a single model. The present invention also modifies the synthesis model based on an estimate of the current input signal to improve the perceptual quality of the speech and background noise under a variety of input conditions. The present invention also improves the voicing dependent spectral estimation algorithm robustness by introducing the use of a Multi-Layer Neural Network in the estimation process. The voicing dependent spectral estimation algorithm provides an accurate and robust estimate of the voicing probability under a variety of background noise conditions. This is essential to providing high quality intelligible speech in the presence of background noise.
    Type: Grant
    Filed: August 2, 2000
    Date of Patent: February 10, 2004
    Inventors: Joseph Gerard Aguilar, Juin-Hwey Chen, Vipul Parikh, Xiaoqin Sun
  • Patent number: 6553477
    Abstract: A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: April 22, 2003
    Assignee: Fujitsu Limited
    Inventors: Murali V. Krishna, Vipul Parikh, Michael Butler, Gene Shen, Masahito Kubo