Patents by Inventor Vipul Singhal

Vipul Singhal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260106615
    Abstract: An apparatus comprises a capacitor connected between a bootstrap supply terminal (HB) and a switching terminal (HS) of a bridge driver. The apparatus further comprises an NMOS transistor having its drain terminal and cathode of its body diode both connected to the bootstrap supply terminal. The apparatus further comprises a pair of PMOS transistors coupled in parallel with shared source and drain terminals, wherein their shared source terminal connects to a first power supply (VDD) at a first power supply terminal, wherein their shared drain terminal connects in series to a source terminal of the NMOS transistor. The apparatus further comprises a charge pump capable of generating a second power supply (VCP) at a second power supply terminal, wherein the second power supply is capable of charging the capacitor via the NMOS transistor and the pair of PMOS transistors at a higher voltage than the first power supply.
    Type: Application
    Filed: May 27, 2025
    Publication date: April 16, 2026
    Inventors: Vipul Singhal, Amal Kumar Kundu, Anant Kamath, Pranav K A
  • Publication number: 20260012011
    Abstract: In one example, a circuit includes a first transistor having a first terminal coupled to a first supply voltage source, a second transistor coupled between a second terminal of the first transistor and a ground terminal, and a voltage clamp circuit coupled between the first supply voltage source and the ground terminal. The circuit may further include a first switch coupled between a control terminal of the first transistor and a second supply voltage source, the first switch having a control terminal coupled to the second terminal of the first transistor, a second switch coupled between a control terminal of the second transistor and the second supply voltage source, the second switch having a control terminal coupled to the ground terminal, and a filter coupled between the control terminal of the second transistor and the ground terminal.
    Type: Application
    Filed: March 26, 2025
    Publication date: January 8, 2026
    Inventors: Satish Vemuri, Yang Xiao, Piranave Kaliannagounder Arumugan, Vipul Singhal, Amal Kumar Kundu
  • Patent number: 11004536
    Abstract: Provided herein are methods and arrangements and related cell-free biomolecular breadboards configured to design, build, implement, debug, and/or test a genetic circuit to be operated in a target environment, by testing in a cell-free system under conditions of the target environment, molecular components of the genetic circuit and/or combinations thereof to select the molecular components and/or combinations thereof of a genetic circuit operative in the target environment.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: May 11, 2021
    Assignee: California Institute of Technology
    Inventors: Zachary Z. Sun, Richard M. Murray, Vipul Singhal
  • Publication number: 20170024512
    Abstract: Provided herein are methods and arrangements and related cell-free biomolecular breadboards configured to design, build, implement, debug, and/or test a genetic circuit to be operated in a target environment, by testing in a cell-free system under conditions of the target environment, molecular components of the genetic circuit and/or combinations thereof to select the molecular components and/or combinations thereof of a genetic circuit operative in the target environment.
    Type: Application
    Filed: February 17, 2016
    Publication date: January 26, 2017
    Inventors: Zachary Z. SUN, Richard M. MURRAY, Vipul SINGHAL
  • Patent number: 6853574
    Abstract: Reducing leakage current when a circuit contains a series of CMOS transistors. The probability that each input signal (connecting to the gate terminal of the corresponding CMOS transistor) will be at a logical value which turns off the corresponding CMOS transistor is determined. A CMOS transistor with a high threshold voltage may be connected to receive an input signal with a high probability to reduce the aggregate leakage current in the circuit. The approach may be used in any environments such as synthesis tools and also manual design methodologies.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: February 8, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Vipul Singhal
  • Publication number: 20040125637
    Abstract: Reducing leakage current when a circuit contains a series of CMOS transistors. The probability that each input signal (connecting to the gate terminal of the corresponding CMOS transistor) will be at a logical value which turns off the corresponding CMOS transistor is determined. A CMOS transistor with a high threshold voltage may be connected to receive an input signal with a high probability to reduce the aggregate leakage current in the circuit. The approach may be used in any environments such as synthesis tools and also manual design methodologies.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 1, 2004
    Applicant: Texas Instruments Incorporated
    Inventor: Vipul Singhal