Abstract: Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus.

Abstract: Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus.

Abstract: An efficient back bias (VBB) detection and control circuit make possible a low voltage memory device and includes an on-chip VBB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (−(|2VTP|+VTN)) during power-up and a second voltage level (−|2VTP| during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.

Abstract: An efficient back bias (V.sub.BB) detection and control circuit make possible a low voltage memory device and includes an on-chip V.sub.BB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (-(.vertline.2 VTP.vertline.+VTN)) during power-up and a second voltage level (-.vertline.2 VTP.vertline. during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.

Abstract: In order to minimize the time consuming testing of large (e.g., 4 mega-bit) memory units, the units can be designed with alternate test mechanisms incorporated therein. The design for testability (DFT) techniques used in dynamic random access memories to reduce the time required testing use parallel read/write procedures and similar techniques. The technique of the present invention compares actual data signal output with an expected data signal in parallel resulting in a faster determination of the memory status. The additional apparatus is incorporated in the memory unit in the vicinity of the group of storage cells under test. By appropriate selection of the location and function of the apparatus, the test apparatus can result in a smaller chip size, faster processing operation, and lower power consumption. The DFT technique reduces the time for testing by incorporating parallel read/write procedures along with additional test procedures.