Patents by Inventor Vipul V. Mehta
Vipul V. Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935805Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 12, 2023Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20230245940Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 12, 2023Publication date: August 3, 2023Applicant: Intel CorporationInventors: Rahul JAIN, Kyu Oh LEE, Siddharth K. ALUR, Wei-Lun K. JEN, Vipul V. MEHTA, Ashish DHALL, Sri Chaitra J. CHAVALI, Rahul N. MANEPALLI, Amruthavalli P. ALUR, Sai VADLAMANI
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Patent number: 11664290Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 27, 2021Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20210391232Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Applicant: INTEL CORPORATIONInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Patent number: 11158558Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 29, 2016Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20210111088Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 29, 2016Publication date: April 15, 2021Applicant: INTEL CORPORATIONInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Patent number: 10403578Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.Type: GrantFiled: September 30, 2017Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Digvijay A. Raorane, Vipul V. Mehta
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Patent number: 10373888Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.Type: GrantFiled: December 30, 2016Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Eric J. Li, Vipul V. Mehta, Digvijay A. Raorane
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Patent number: 10290592Abstract: A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.Type: GrantFiled: June 30, 2017Date of Patent: May 14, 2019Assignee: INTEL CORPORATIONInventors: John J Beatty, Suzana Prstic, Vipul V Mehta
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Publication number: 20190103361Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a top surface and a vertical surface extending downward from the top surface. The top surface and the vertical surface can define an edge. The electronic device package can also include an electronic component disposed on the top surface of the substrate and electrically coupled to the substrate. In addition, the electronic device package can include an underfill material disposed at least partially between the electronic component and the top surface of the substrate. A lateral portion of the underfill material can extend from the electronic component to at least the edge. Associated systems and methods are also disclosed.Type: ApplicationFiled: September 30, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: Digvijay A. Raorane, Vipul V. Mehta
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Publication number: 20190006293Abstract: A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: John J Beatty, Suzana Prstic, Vipul V Mehta
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Publication number: 20180190560Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Applicant: Intel CorporationInventors: Eric J. Li, Vipul V. Mehta, Digvijay A. Raorane
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Patent number: 8895365Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.Type: GrantFiled: August 31, 2012Date of Patent: November 25, 2014Assignee: Intel CorporationInventors: Suriyakala Ramalingam, Rajen S. Sidhu, Nisha Ananthakrishnan, Sivakumar Nagarajan, Wei Tan, Sandeep Razdan, Vipul V. Mehta
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Publication number: 20140061902Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 31, 2012Publication date: March 6, 2014Inventors: Suriyakala Ramalingam, Rajen S. Sidhu, Nisha Ananthakrishnan, Sivakumar Nagarajan, Wei Tan, Sandeep Razdan, Vipul V. Mehta