Patents by Inventor Viraj Sardesai
Viraj Sardesai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10978566Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.Type: GrantFiled: January 15, 2020Date of Patent: April 13, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Hui Zang, Guowei Xu, Keith Tabakman, Viraj Sardesai
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Publication number: 20200152749Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Hui ZANG, Guowei XU, Keith TABAKMAN, Viraj SARDESAI
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Patent number: 10580875Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.Type: GrantFiled: January 17, 2018Date of Patent: March 3, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Guowei Xu, Keith Tabakman, Viraj Sardesai
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Publication number: 20190221650Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.Type: ApplicationFiled: January 17, 2018Publication date: July 18, 2019Inventors: Hui ZANG, Guowei XU, Keith TABAKMAN, Viraj SARDESAI
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Publication number: 20180277427Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.Type: ApplicationFiled: May 24, 2018Publication date: September 27, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
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Patent number: 10043708Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.Type: GrantFiled: November 9, 2016Date of Patent: August 7, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Viraj Sardesai, Suraj K. Patil, Scott Beasor, Vimal Kumar Kamineni
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Publication number: 20180166402Abstract: A semiconductor device includes a metal thin film such as an eFUSE or a precision resistor above and laterally displaced from an interconnect structure. A first dielectric layer is disposed over the interconnect structure and optionally under the metal thin film, and is adapted to prevent etching of the interconnect structure during patterning of the metal thin film. Contacts to the metal thin film and the interconnect are made through a second dielectric layer that is disposed over the metal thin film and over the interconnect.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Viraj SARDESAI, William HENSON, Domingo FERRER LUPPI, Scott ALLEN, Emre ALPTEKIN
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Patent number: 9997411Abstract: Embodiments of present disclosure provide methods of forming a resistor. One such method can include forming a first transistor structure and a second transistor structure on a semiconductor substrate, wherein the first transistor structure includes a dummy gate thereon; forming a mask on the first transistor structure; forming a metal gate on the second transistor structure; removing the mask, after the forming of the metal gate, to expose the first transistor structure; and siliciding a top portion of the dummy gate of the first transistor structure to yield a resistor.Type: GrantFiled: August 27, 2015Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Cung Tran, Emre Alptekin, Viraj Sardesai, Reinaldo Vega
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Publication number: 20180130703Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.Type: ApplicationFiled: November 9, 2016Publication date: May 10, 2018Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
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Publication number: 20180130702Abstract: Structures that include cobalt metallization and methods of forming such structures. A feature is located inside an opening in a dielectric layer and a cap layer located on a top surface of the feature. The feature is composed of cobalt, and the cap layer is composed of ruthenium or a cobalt-containing alloy.Type: ApplicationFiled: November 8, 2016Publication date: May 10, 2018Inventors: Suraj K. Patil, Viraj Sardesai
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Patent number: 9312185Abstract: Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a semiconductor substrate in a replacement-metal-gate process to have, respectively, a sacrificial gate and spacers adjacent to sidewalls of the sacrificial gate; covering the second structure with an etch-stop mask; replacing the sacrificial gate of the first structure with a replacement metal gate; removing the etch-stop mask to expose the sacrificial gate of the second structure; forming a silicide in the second structure as a metal resistor; and forming contacts to the silicide. In one embodiment, forming the silicide includes siliciding a top portion of the sacrificial gate of the second structure to form the metal resistor. In another embodiment, forming the silicide includes removing the sacrificial gate of the second structure to expose and silicide a channel region underneath thereof.Type: GrantFiled: May 6, 2014Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: Cung Tran, Emre Alptekin, Viraj Sardesai, Reinaldo Vega
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Patent number: 9305835Abstract: Embodiments of present invention provide a method of forming air spacers in a transistor structure. The method includes forming a gate structure of a transistor on top of a semiconductor substrate; forming a first and a second disposable spacers adjacent to a first and a second sidewall of the gate structure; forming a first and a second conductive studs next to the first and the second disposable spacer; removing the first and second disposable spacers to create empty spaces between the first and second conductive studs and the gate structure; and preserving the empty spaces by forming dielectric plugs at a top of the empty spaces.Type: GrantFiled: February 26, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Emre Alptekin, Viraj Sardesai, Cung Tran, Reinaldo Vega
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Publication number: 20150364419Abstract: Embodiments of present disclosure provide methods of forming a resistor. One such method can include forming a first transistor structure and a second transistor structure on a semiconductor substrate, wherein the first transistor structure includes a dummy gate thereon; forming a mask on the first transistor structure; forming a metal gate on the second transistor structure; removing the mask, after the forming of the metal gate, to expose the first transistor structure; and siliciding a top portion of the dummy gate of the first transistor structure to yield a resistor.Type: ApplicationFiled: August 27, 2015Publication date: December 17, 2015Inventors: Cung Tran, Emre Alptekin, Viraj Sardesai, Reinaldo Vega
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Publication number: 20150325483Abstract: Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a semiconductor substrate in a replacement-metal-gate process to have, respectively, a sacrificial gate and spacers adjacent to sidewalls of the sacrificial gate; covering the second structure with an etch-stop mask; replacing the sacrificial gate of the first structure with a replacement metal gate; removing the etch-stop mask to expose the sacrificial gate of the second structure; forming a silicide in the second structure as a metal resistor; and forming contacts to the silicide. In one embodiment, forming the silicide includes siliciding a top portion of the sacrificial gate of the second structure to form the metal resistor. In another embodiment, forming the silicide includes removing the sacrificial gate of the second structure to expose and silicide a channel region underneath thereof.Type: ApplicationFiled: May 6, 2014Publication date: November 12, 2015Applicant: International Business Machines CorporationInventors: Cung Tran, Emre Alptekin, Viraj Sardesai, Reinaldo Vega
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Publication number: 20150243544Abstract: Embodiments of present invention provide a method of forming air spacers in a transistor structure. The method includes forming a gate structure of a transistor on top of a semiconductor substrate; forming a first and a second disposable spacers adjacent to a first and a second sidewall of the gate structure; forming a first and a second conductive studs next to the first and the second disposable spacer; removing the first and second disposable spacers to create empty spaces between the first and second conductive studs and the gate structure; and preserving the empty spaces by forming dielectric plugs at a top of the empty spaces.Type: ApplicationFiled: February 26, 2014Publication date: August 27, 2015Applicant: International Business Machines CorporationInventors: Emre Alptekin, Viraj Sardesai, Cung Tran, Reinaldo Vega
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Publication number: 20070249133Abstract: A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.Type: ApplicationFiled: April 11, 2006Publication date: October 25, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary Bronner, David Fried, Jeffrey Gambino, Leland Chang, Ramachandra Divakaruni, Haizhou Yin, Gregory Costrini, Viraj Sardesai
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Publication number: 20050017282Abstract: In the process of forming a trench capacitor, the conductive strap connecting the center electrode of the capacitor with a circuit element in the substrate, such as the pass transistor of a DRAM cell, is separated from the crystalline substrate material by a barrier layer of silicon carbide formed during the process of etching the material within the trench, such as an oxide collar, using a reactive ion etch process with an etchant gas that contains carbon, such as C4F8.Type: ApplicationFiled: July 25, 2003Publication date: January 27, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Dobuzinsky, Jonathan Faltermeier, Philip Flaitz, Rajarao Jammy, Yuko Ninomiya, Ravikumar Ramachandran, Viraj Sardesai, Yun Wang
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Patent number: 6504210Abstract: A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.Type: GrantFiled: June 23, 2000Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Jeffrey Peter Gambino, Jack A. Mandelman, Viraj Sardesai, Mary Elizabeth Weybright
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Patent number: 6268293Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C4F8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.Type: GrantFiled: November 18, 1999Date of Patent: July 31, 2001Assignees: International Business Machines Corporation, Infineon Technologies North American CorporationInventors: Lawrence Clevenger, Greg Costrini, Dave Dobuzinsky, Yoichi Otani, Thomas Rupp, Viraj Sardesai
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Patent number: 5401677Abstract: An improved process for the formation of high quality, high yield platinum silicides on silicon wafers uses a post sputter platinum deposition and high vacuum bake to complete the first step of silicide reaction, resulting in Pt.sub.2 Si formation before sinter. This additional process step is then followed by a 500.degree. to 900.degree. C. sinter. The use of a high vacuum bake provides easy control of O.sub.2 and H.sub.2 O impurities. The vacuum bake can be done in any high vacuum tool. The bake temperatures range from 200.degree. to 450.degree. C. at 5.times.10.sup.-6 torr, with an in-situ bake time of 3 to 5 minutes or an ex-situ bake time of 10 to 30 minutes, depending on batch size or tool. A particular advantage of the process is that it can be performed in existing tools.Type: GrantFiled: December 23, 1993Date of Patent: March 28, 1995Assignee: International Business Machines CorporationInventors: Robert D. Bailey, Cyril Cabral, Jr., Brian Cunningham, Hormazdyar M. Dalal, James M. Harper, Viraj Sardesai, Horatio S. Wildman, Thomas O. Williams