Abstract: Systems which progress through a series of states or program steps, such as software controlled computers, are monitored by means of a watchdog timer which samples at least two check bits generated by a system being monitored with the check bits being generated such that only one can change its logic state between valid samples of the check bits. The monitored system is reset if a fault within the system results in an error in the normal sequence through the series of states or program steps such that more than one of the check bits changes from sample to sample. In addition, if the sequence becomes static such that no bits change within the check bits from sample to sample, a time-out will occur which also resets the monitored system. Preferably, the check bits are generated in accordance with Gray code.